Behavioral Architecture Reference

Components
VMECONFREGS	<Entity VMECONFREGS>
CFEBJTAG	<Entity CFEBJTAG>
VMEMON	<Entity VMEMON>
SPI_PORT	<Entity SPI_PORT>
SYSTEM_MON	<Entity SYSTEM_MON>
LVDBMON	<Entity LVDBMON>
SYSTEM_TEST	<Entity SYSTEM_TEST>
COMMAND_MODULE	<Entity COMMAND_MODULE>
SPI_CTRL	<Entity SPI_CTRL>

Constants
bw_data	integer := 16
num_dev	integer := 9

Types
dev_data_array	is array ( 0 to num_dev ) of std_logic_vector ( 15 downto 0 )

Signals
device	std_logic_vector ( num_dev downto 0 ) := ( others = > ' 0 ' )
cmd	std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
strobe	std_logic := ' 0 '
tovme_b	std_logic := ' 0 '
doe_b	std_logic := ' 0 '
vme_data_out_buf	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
outdata_dev	dev_data_array
dtack_dev	std_logic_vector ( num_dev downto 0 ) := ( others = > ' 0 ' )
idx_dev	integer range 0 to num_dev
devout	std_logic_vector ( bw_data - 1 downto 0 ) := ( others = > ' 0 ' )
diagout_buf	std_logic_vector ( 17 downto 0 ) := ( others = > ' 0 ' )
led_cfebjtag	std_logic := ' 0 '
led_command	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
dl_jtag_tck_inner	std_logic_vector ( 6 downto 0 )
dl_jtag_tdi_inner	std_logic
dl_jtag_tms_inner	std_logic
cmd_adrs_inner	std_logic_vector ( 17 downto 2 ) := ( others = > ' 0 ' )
odmb_id_inner	std_logic_vector ( 15 downto 0 )
alct	std_logic_vector ( 17 downto 0 )
otmb_tx	std_logic_vector ( 48 downto 0 )
otmb_rx	std_logic_vector ( 5 downto 0 )
otmb_lct_rqst	std_logic
otmb_ext_trig	std_logic
cafifo_l1a	std_logic := ' 0 '
cafifo_l1a_match_in	std_logic_vector ( NCFEB + 2 downto 1 ) := ( others = > ' 0 ' )
spi_cfg_ul_pulse	std_logic := ' 0 '
spi_const_ul_pulse	std_logic := ' 0 '
spi_reg_in	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
spi_cfg_busy	std_logic := ' 0 '
spi_const_busy	std_logic := ' 0 '
spi_cfg_reg_we	integer range 0 to NREGS := 0
spi_const_reg_we	integer range 0 to NREGS := 0
spi_const_regs	cfg_regs_array
spi_cfg_regs	cfg_regs_array
spi_rst	std_logic := ' 0 '
spi_ctrl_rst	std_logic := ' 0 '
spi_enable	std_logic := ' 0 '
spi_disable	std_logic := ' 0 '
spi_cmd_fifo_write_en	std_logic := ' 0 '
spi_cmd_fifo_in	std_logic_vector ( 15 downto 0 ) := x " 0000 "
spi_readback_fifo_read_en	std_logic := ' 0 '
spi_readback_fifo_out	std_logic_vector ( 15 downto 0 ) := x " 0000 "
spi_read_busy	std_logic := ' 0 '
spi_rbk_wrd_cnt	std_logic_vector ( 10 downto 0 ) := " 00000000000 "
spi_timer	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
spi_status	std_logic_vector ( 15 downto 0 ) := x " 0000 "

Instantiations
dev1_cfebjtag	CFEBJTAG <Entity CFEBJTAG>
dev3_vmemon	VMEMON <Entity VMEMON>
dev4_vmeconfregs	VMECONFREGS <Entity VMECONFREGS>
dev6_spi_port_i	SPI_PORT <Entity SPI_PORT>
dev7_sysmon	SYSTEM_MON <Entity SYSTEM_MON>
dev8_lvdbmon	LVDBMON <Entity LVDBMON>
dev9_systest	SYSTEM_TEST <Entity SYSTEM_TEST>
command_pm	COMMAND_MODULE <Entity COMMAND_MODULE>
spi_ctrl_i	SPI_CTRL <Entity SPI_CTRL>

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The documentation for this class was generated from the following file:

• /homes/oshiro/odmb/firmware/odmb7_ucsb_dev/source/odmb_vme/odmb_vme.vhd