VMECONFREGS Entity Reference

module for interacting with configuration and constant registers loaded from nonvolatile memory More...

Inheritance diagram for VMECONFREGS:

Entities
VMECONFREGS_Arch	architecture

Libraries
ieee
work
unisim

Use Clauses
unisim.vcomponents.all
ieee.std_logic_1164.all
ieee.std_logic_unsigned.all
ieee.numeric_std.all
ieee.std_logic_misc.all
work.ucsb_types.all

Generics
NCFEB	integer range 1 to 7 := 7

Ports
SLOWCLK	in std_logic
	2.5 MHz clock input
CLK	in std_logic
	40 MHz clock input
RST	in std_logic
	Soft reset signal.
DEVICE	in std_logic
	Indicates whether this is the selected VME device.
STROBE	in std_logic
	Indicates VME command is ready to be executed.
COMMAND	in std_logic_vector ( 9 downto 0 )
	VME command to be executed (x"4" & COMMAND & "00" is user-readable version)
WRITER	in std_logic
	Indicates if VME command is a read or write command.
DTACK	out std_logic
	Data acknowledge to be sent once command is initialized/executed.
INDATA	in std_logic_vector ( 15 downto 0 )
	Input data from VME backplane.
OUTDATA	out std_logic_vector ( 15 downto 0 )
	Output data to VME backplane.
LCT_L1A_DLY	out std_logic_vector ( 5 downto 0 )
	Configuration register controlling LCT delay in CALIBTRG.
CABLE_DLY	out integer range 0 to 1
	CFG register controlling delay for DCFEB bound signals (L1A,L1A_MATCH,RESYNC,BC0) in top level.
OTMB_PUSH_DLY	out integer range 0 to 63
	CFG register controlling delay between OTMBDAV and pushing to the FIFO in TRGCNTRL.
ALCT_PUSH_DLY	out integer range 0 to 63
	CFG register controlling delay between ALCTDAV and pushing to the FIFO in TRGCNTRL.
BX_DLY	out integer range 0 to 4095
	CFG register that would be used in counting bunch crossings in CAFIFO, but actually unused.
INJ_DLY	out std_logic_vector ( 4 downto 0 )
	CFG register controlling delay for calibration INJPULSE in CALIBTRG.
EXT_DLY	out std_logic_vector ( 4 downto 0 )
	CFG register controlling delay for calibration EXTPULSE in CALIBTRG.
CALLCT_DLY	out std_logic_vector ( 3 downto 0 )
	CFG register controlling delay for calibration LCT in CALIBTRG.
ODMB_ID	out std_logic_vector ( 15 downto 0 )
	CONST register storing the unique ODMB ID.
NWORDS_DUMMY	out std_logic_vector ( 15 downto 0 )
	CFG register controlling the number of words generated by dummy DCFEBs/ALCT/OTMB.
KILL	out std_logic_vector ( NCFEB + 2 downto 1 )
	CFG register controlling which boards (ALCT/OTMB/DCFEBs) should be ignored.
CRATEID	out std_logic_vector ( 7 downto 0 )
	CFG register withe crate ID, used by CONTROL_FSM in packet generation.
CHANGE_REG_DATA	in std_logic_vector ( 15 downto 0 )
	Signal to set new value for KILL register n case of auto-kill.
CHANGE_REG_INDEX	in integer range 0 to NREGS
	Signal to enable writing to CFG registers, only ever 7(for setting KILL) or NREGS(none)
SPI_CFG_UL_PULSE	in std_logic
	Signal from SPI_PORT to write CFG registers from PROM contents.
SPI_CONST_UL_PULSE	in std_logic
	Signal from SPI_PORT to write CONST registers from PROM contents.
SPI_REG_IN	in std_logic_vector ( 15 downto 0 )
	CFG or CONST register contents to be written, from SPI_PORT.
SPI_CFG_BUSY	in std_logic
	From SPI_PORT, indicates CFG register upload in progress.
SPI_CONST_BUSY	in std_logic
	From SPI_PORT, indicates CONST register upload in progress.
SPI_CFG_REG_WE	in integer range 0 to NREGS
	Write enable for each CFG register, from SPI_PORT.
SPI_CONST_REG_WE	in integer range 0 to NREGS
	Write enable for each CONST register, from SPI_PORT.
SPI_CFG_REGS	out cfg_regs_array
	Contents of CFG registers, used by SPI_PORT to save to PROM.
SPI_CONST_REGS	out cfg_regs_array
	Contents of CONST registers, used by SPI_PORT to save to PROM.

Detailed Description

module for interacting with configuration and constant registers loaded from nonvolatile memory

Supported VME commands:

• W/R 40YZ read configuration register YZ/4
• R 4Y00 read constant register Y-1
• W/R 4FFC read constant register write mask (W disabled in most fw versions) The specific quantities stored in the configuration and constant registers are CFG register 0 (4000) LCT_L1A_DLY[5:0] LCT/L1A gap - 100 CFG register 1 (4004) OTMB_PUSH_DLY[5:0] L1A/OTMBDAV gap, read with "R 338C" CFG register 2 (4008) CABLE_DLY[0:0] delays L1A[_MATCH], RESYNC, BC0 by 25 ns CFG register 3 (400C) ALCT_DLY[5:0] L1A/ALCTDAV gap, read with "R 339C" CFG register 4 (4010) INJ_DLY[4:0] delay for INJPLS in units of 12.5 ns CFG register 5 (4014) EXT_DLY[4:0] delay for EXTPLS in units of 12.5 ns CFG reguster 6 (4018) CALLCT_DLY[3:0] delay for calibration LCT in units of 25 ns CFG register 7 (401C) KILL[9:1] for masking other boards (ALCT,TMB,7DCFEBs) CFG register 8 (4020) CRATEID[6:0] CFG register 9 (4024) Firmware ID, not writeable CFG register 10 (4028) NWORDS_DUMMY[15:0] number of words generated by simulated FE boards CFG register 11 (402C) BX_DLY[11:0] bunch crossing counter delay, unused CONST register 0 (4100) ODMB unique ID CONST register 1 (4200) Firmware version CONST register 2 (4300) Firmware build CONST register 3 (4400) Month/day firmware was synthesized CONST register 4 (4500) Year firmware was synthesized

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The documentation for this class was generated from the following file:

• /homes/oshiro/odmb/firmware/odmb7_ucsb_dev/source/odmb_vme/vmeconfregs.vhd