ODMB7_UCSB_DEV
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LVDBMON Entity Reference

VME device that monitors voltages on LVMB and powers on/off DCFEBs+ALCT. More...

Inheritance diagram for LVDBMON:
ODMB_VME odmb7_ucsb_dev

Entities

LVDBMON_Arch  architecture
 

Libraries

ieee 
work 
unisim 

Use Clauses

ieee.std_logic_1164.all 
ieee.numeric_std.all 
work.ucsb_types.all 
work.Latches_Flipflops.all 
unisim.vcomponents.all 

Ports

SLOWCLK   in std_logic
 1.25 MHz clock input
RST   in std_logic
 Reset signal.
PON_RESET   in std_logic
 Power on reset, unused.
DEVICE   in std_logic
 Indicates whether this is the selected VME device.
STROBE   in std_logic
 Indicates VME command is ready to be executed.
COMMAND   in std_logic_vector ( 9 downto 0 )
 VME command to be executed (x"8" & COMMAND & "00" is user-readable version)
WRITER   in std_logic
 Indicates if VME command is read or write.
INDATA   in std_logic_vector ( 15 downto 0 )
 Input data from VME backplane.
OUTDATA   out std_logic_vector ( 15 downto 0 )
 Output data to VME backplane.
DTACK   out std_logic
 Data acknowledge to be sent once command is initialized/executed.
LVADCEN   out std_logic_vector ( 6 downto 0 )
 SPI chip select signal to ADCs.
ADCCLK   out std_logic
 SPI clock signal to ADCs.
ADCDATA   out std_logic
 SPI data signal to ADCs.
ADCIN   in std_logic
 SPI data signal from ADCs.
LVTURNON   out std_logic_vector ( 8 downto 1 )
 Power-on signal to LVMB.
R_LVTURNON   in std_logic_vector ( 8 downto 1 )
 Read-back power-on signal from LVMB.
LOADON   out std_logic
 Signal to load power-on signals.
DIAGOUT   out std_logic_vector ( 17 downto 0 )
 Debugging signal.

Detailed Description

VME device that monitors voltages on LVMB and powers on/off DCFEBs+ALCT.

Supported VME commands:


The documentation for this class was generated from the following file: