VME device controlling access to ODMB board monitoring (currents, voltages, temperature) More...

Inheritance diagram for SYSTEM_MON:

Ports
OUTDATA	out std_logic_vector ( 15 downto 0 )
	Output data to VME backplane.
DTACK	out std_logic
	Data acknowledge to VME backplane.
ADC_CS_B	out std_logic_vector ( 4 downto 0 )
	SPI chip select to ADCs.
ADC_DIN	out std_logic
	SPI input to ADCs.
ADC_SCK	out std_logic
	SPI clock to ADCs.
ADC_DOUT	in std_logic
	SPI output from ADCs.
SLOWCLK	in std_logic
	1.25 MHz clock
FASTCLK	in std_logic
	40 MHz clock
RST	in std_logic
	Soft reset.
DEVICE	in std_logic
	Indicates if this is the selected VME device.
STROBE	in std_logic
	Indicates VME command ready.
COMMAND	in std_logic_vector ( 9 downto 0 )
	VME command.
WRITER	in std_logic
	Indicates if a command is read (1) or write (0)
VAUXP	in std_logic_vector ( 15 downto 0 )
	Current monitoring analog signals.
VAUXN	in std_logic_vector ( 15 downto 0 )
	Current monitoring analog signals.

Detailed Description

VME device controlling access to ODMB board monitoring (currents, voltages, temperature)

Supported VME commands:

R 7XY0 read SYSMON channel XY (see below) - current is result*10 channels 0 and 9 and result*5 for others
W 73Y0 load data from ADC chip Y (chip 0-4)
R 74Y0 read loaded ADC for channel Y (channels 1-8) - number is voltage/1000

The documentation for this class was generated from the following file:

Entities