Behavioral Architecture Reference

Processes
proc_sync_l1acnt	( cmsclk )
done_fsm_regs	( done_next_state , pon_reset , sysclk10 )
done_fsm_logic	( done_current_state , DCFEB_DONE , done_cnt )
odmb_status_pro	( cmsclk )

Components
odmb_clocking	<Entity odmb_clocking>
ODMB_VME	<Entity ODMB_VME>
ODMB_CTRL	<Entity ODMB_CTRL>
LCTDLY	<Entity LCTDLY>

Constants
NCFEB	integer range 1 to 7 := 7
SPY_SEL	std_logic := ' 1 '
SPY_NLINK	integer := 1
SPYDWIDTH	integer := 16
DDU_NTXLINK	integer := 4
DDU_NRXLINK	integer := 4
DDUTXDWIDTH	integer := 16
DDURXDWIDTH	integer := 16
ALCT_NLINK	integer := 1
ALCTDWIDTH	integer := 16

Signals
mgtrefclk0_224	std_logic
mgtrefclk0_225	std_logic
mgtrefclk0_226	std_logic
mgtrefclk1_226	std_logic
mgtrefclk0_227	std_logic
mgtrefclk1_227	std_logic
sysclk625k	std_logic
sysclk1p25	std_logic
sysclk2p5	std_logic
sysclk10	std_logic
sysclk20	std_logic
sysclk40	std_logic
sysclk80	std_logic
cmsclk	std_logic
clk_emcclk	std_logic
clk_lfclk	std_logic
clk_gp6	std_logic
clk_gp7	std_logic
mgtclk1	std_logic
mgtclk2	std_logic
mgtclk3	std_logic
mgtclk4	std_logic
mgtclk5	std_logic
mgtclk125	std_logic
vme_dir_b	std_logic
vme_dir	std_logic
vme_oe_b	std_logic
vme_data_out_buf	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
vme_data_in_buf	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
rst	std_logic := ' 0 '
dcfeb_tck	std_logic_vector ( NCFEB downto 1 ) := ( others = > ' 0 ' )
dcfeb_tms	std_logic := ' 0 '
dcfeb_tdi	std_logic := ' 0 '
dcfeb_tdo	std_logic_vector ( NCFEB downto 1 ) := ( others = > ' 0 ' )
reset_pulse	std_logic := ' 0 '
reset_pulse_q	std_logic := ' 0 '
l1acnt_rst	std_logic := ' 0 '
l1acnt_rst_meta	std_logic := ' 0 '
l1acnt_rst_sync	std_logic := ' 0 '
l1a_reset_pulse	std_logic := ' 0 '
l1a_reset_pulse_q	std_logic := ' 0 '
opt_reset_pulse	std_logic := ' 0 '
opt_reset_pulse_q	std_logic := ' 0 '
premask_injpls	std_logic := ' 0 '
premask_extpls	std_logic := ' 0 '
dcfeb_injpls	std_logic := ' 0 '
dcfeb_extpls	std_logic := ' 0 '
test_bc0	std_logic := ' 0 '
pre_bc0	std_logic := ' 0 '
dcfeb_bc0	std_logic := ' 0 '
dcfeb_resync	std_logic := ' 0 '
dcfeb_l1a	std_logic := ' 0 '
masked_l1a	std_logic := ' 0 '
odmbctrl_l1a	std_logic := ' 0 '
dcfeb_l1a_match	std_logic_vector ( NCFEB downto 1 ) := ( others = > ' 0 ' )
masked_l1a_match	std_logic_vector ( NCFEB downto 1 ) := ( others = > ' 0 ' )
odmbctrl_l1a_match	std_logic_vector ( NCFEB downto 1 ) := ( others = > ' 0 ' )
ccb_bx0	std_logic := ' 0 '
ccb_bx0_q	std_logic := ' 0 '
pon_rst_reg	std_logic_vector ( 31 downto 0 ) := x " 00FFFFFF "
pon_reset	std_logic := ' 0 '
done_cnt_en	std_logic_vector ( NCFEB downto 1 )
done_cnt_rst	std_logic_vector ( NCFEB downto 1 )
done_cnt	t_done_cnt_arr ( NCFEB downto 1 )
done_next_state	t_done_state_arr ( NCFEB downto 1 )
done_current_state	t_done_state_arr ( NCFEB downto 1 )
dcfeb_done_pulse	std_logic_vector ( NCFEB downto 1 ) := ( others = > ' 0 ' )
dcfeb_initjtag	std_logic := ' 0 '
dcfeb_initjtag_d	std_logic := ' 0 '
dcfeb_initjtag_dd	std_logic := ' 0 '
ccb_cmd_bxev	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
ccb_cmd_reg	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
ccb_data_reg	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
ccb_rsv	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
ccb_other	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
ccb_rsv_reg	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
ccb_other_reg	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
ccb_rsv_reg_b	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
ccb_other_reg_b	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
lvmb_sdout	std_logic := ' 0 '
test_lct	std_logic := ' 0 '
test_l1a	std_logic := ' 0 '
raw_l1a	std_logic := ' 0 '
raw_lct	std_logic_vector ( NCFEB downto 0 )
mask_pls	std_logic := ' 0 '
mask_l1a	std_logic_vector ( NCFEB downto 0 ) := ( others = > ' 0 ' )
lct_l1a_dly	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
inj_dly	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
ext_dly	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
callct_dly	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
cable_dly	integer range 0 to 1
odmb_ctrl_reg	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
kill	std_logic_vector ( NCFEB + 2 downto 1 ) := ( others = > ' 0 ' )
change_reg_data	std_logic_vector ( 15 downto 0 )
change_reg_index	integer range 0 to NREGS := NREGS
test_inj	std_logic := ' 0 '
test_pls	std_logic := ' 0 '
test_ped	std_logic := ' 0 '
goodcrc_cnt	t_twobyte_arr ( NCFEB downto 1 )
dcfeb_bad_rx_cnt	t_twobyte_arr ( NCFEB downto 1 )
dcfeb_dvalid_cnt	t_twobyte_arr ( NCFEB downto 1 )
into_cafifo_dav_cnt	t_twobyte_arr ( NCFEB + 2 downto 1 )
l1a_match_cnt	t_twobyte_arr ( NCFEB + 2 downto 1 )
cnfg_data_in	std_logic_vector ( 7 downto 4 ) := ( others = > ' 0 ' )
cnfg_data_out	std_logic_vector ( 7 downto 4 ) := ( others = > ' 0 ' )
cnfg_data_dir	std_logic_vector ( 7 downto 4 ) := ( others = > ' 0 ' )
fw_reset	std_logic := ' 0 '
fw_reset_q	std_logic := ' 0 '
opt_reset	std_logic := ' 0 '
opt_reset_q	std_logic := ' 0 '
ccb_softrst_b_q	std_logic := ' 1 '
fw_rst_reg	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
opt_rst_reg	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
reset	std_logic := ' 0 '
mgt_prbs_type	std_logic_vector ( 3 downto 0 )
dcfeb_prbs_fiber_sel	std_logic_vector ( 3 downto 0 )
dcfeb_prbs_en	std_logic
dcfeb_prbs_rst	std_logic
dcfeb_prbs_rd_en	std_logic
dcfeb_rxprbserr	std_logic
usrclk_spy_tx	std_logic
usrclk_spy_rx	std_logic
spy_rx_n	std_logic
spy_rx_p	std_logic
spy_txready	std_logic
spy_rxready	std_logic
spy_txdata	std_logic_vector ( 15 downto 0 )
spy_txd_valid	std_logic_vector ( SPY_NLINK - 1 downto 0 )
spy_txdiffctrl	std_logic_vector ( 3 downto 0 )
spy_loopback	std_logic_vector ( 2 downto 0 )
spy_rxdata	std_logic_vector ( 15 downto 0 )
spy_rxd_valid	std_logic_vector ( SPY_NLINK - 1 downto 0 )
spy_bad_rx	std_logic_vector ( SPY_NLINK - 1 downto 0 )
spy_reset	std_logic
spy_prbs_tx_en	std_logic_vector ( SPY_NLINK - 1 downto 0 )
spy_prbs_rx_en	std_logic_vector ( SPY_NLINK - 1 downto 0 )
spy_prbs_tst_cnt	std_logic_vector ( 15 downto 0 )
spy_prbs_err_cnt	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
usrclk_ddu_tx	std_logic
usrclk_ddu_rx	std_logic
ddu_txdata1	std_logic_vector ( DDUTXDWIDTH - 1 downto 0 )
ddu_txdata2	std_logic_vector ( DDUTXDWIDTH - 1 downto 0 )
ddu_txdata3	std_logic_vector ( DDUTXDWIDTH - 1 downto 0 )
ddu_txdata4	std_logic_vector ( DDUTXDWIDTH - 1 downto 0 )
ddu_txd_valid	std_logic_vector ( DDU_NTXLINK downto 1 )
ddu_rxdata1	std_logic_vector ( DDURXDWIDTH - 1 downto 0 )
ddu_rxdata2	std_logic_vector ( DDURXDWIDTH - 1 downto 0 )
ddu_rxdata3	std_logic_vector ( DDURXDWIDTH - 1 downto 0 )
ddu_rxdata4	std_logic_vector ( DDURXDWIDTH - 1 downto 0 )
ddu_rxd_valid	std_logic_vector ( DDU_NRXLINK downto 1 )
ddu_bad_rx	std_logic_vector ( DDU_NRXLINK downto 1 )
ddu_rxready	std_logic
ddu_txready	std_logic
ddu_reset	std_logic
ddu_prbs_tx_en	std_logic_vector ( 4 downto 1 )
ddu_prbs_rx_en	std_logic_vector ( 4 downto 1 )
ddu_prbs_tst_cnt	std_logic_vector ( 15 downto 0 )
ddu_prbs_err_cnt	std_logic_vector ( 15 downto 0 )
usrclk_mgtc	std_logic
dcfeb1_data	std_logic_vector ( 15 downto 0 )
dcfeb2_data	std_logic_vector ( 15 downto 0 )
dcfeb3_data	std_logic_vector ( 15 downto 0 )
dcfeb4_data	std_logic_vector ( 15 downto 0 )
dcfeb5_data	std_logic_vector ( 15 downto 0 )
dcfeb6_data	std_logic_vector ( 15 downto 0 )
dcfeb7_data	std_logic_vector ( 15 downto 0 )
dcfeb_rxd_valid	std_logic_vector ( NCFEB downto 1 )
dcfeb_crc_valid	std_logic_vector ( NCFEB downto 1 )
dcfeb_bad_rx	std_logic_vector ( NCFEB downto 1 )
dcfeb_rxready	std_logic
mgtc_reset	std_logic
dcfeb_prbs_rx_en	std_logic_vector ( NCFEB downto 1 )
dcfeb_prbs_tst_cnt	std_logic_vector ( 15 downto 0 )
dcfeb_prbs_err_cnt	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
dcfeb_datafifo_full	std_logic_vector ( NCFEB downto 1 ) := ( others = > ' 0 ' )
dcfeb_datafifo_afull	std_logic_vector ( NCFEB downto 1 ) := ( others = > ' 0 ' )
usrclk_mgta	std_logic
alct_rxdata	std_logic_vector ( 15 downto 0 )
alct_rxd_valid	std_logic_vector ( ALCT_NLINK - 1 downto 0 )
alct_bad_rx	std_logic_vector ( ALCT_NLINK - 1 downto 0 )
alct_rxready	std_logic
mgta_data_valid	std_logic_vector ( 4 downto 1 )
mgta_bad_rx	std_logic_vector ( 4 downto 1 )
mgta_rxready	std_logic
mgta_reset	std_logic
mgt_reset	std_logic := ' 0 '
alct_prbs_rx_en	std_logic_vector ( ALCT_NLINK - 1 downto 0 )
alct_prbs_tst_cnt	std_logic_vector ( 15 downto 0 )
alct_prbs_err_cnt	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
daq8_rxdata	std_logic_vector ( 15 downto 0 )
daq9_rxdata	std_logic_vector ( 15 downto 0 )
daq10_rxdata	std_logic_vector ( 15 downto 0 )
nwords_dummy	std_logic_vector ( 15 downto 0 )
diagout_inner	std_logic_vector ( 17 downto 0 ) := ( others = > ' 0 ' )
odmb_data	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
odmb_data_sel	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )

Attributes
clock_buffer_type	string
clock_buffer_type	CCB_CMD : signal is " NONE "
clock_buffer_type	CCB_CMD_S : signal is " NONE "
clock_buffer_type	CCB_DATA : signal is " NONE "
clock_buffer_type	CCB_DATA_S : signal is " NONE "
clock_buffer_type	CCB_CAL : signal is " NONE "
clock_buffer_type	CCB_CRSV : signal is " NONE "
clock_buffer_type	CCB_DRSV : signal is " NONE "
clock_buffer_type	CCB_RSVO : signal is " NONE "
clock_buffer_type	CCB_RSVI : signal is " NONE "
clock_buffer_type	CCB_BX0_B : signal is " NONE "
clock_buffer_type	CCB_BX_RST_B : signal is " NONE "
clock_buffer_type	CCB_L1A_RST_B : signal is " NONE "
clock_buffer_type	CCB_L1A_B : signal is " NONE "
clock_buffer_type	CCB_L1A_RLS : signal is " NONE "
clock_buffer_type	CCB_CLKEN : signal is " NONE "
clock_buffer_type	CCB_EVCNTRES_B : signal is " NONE "

Instantiations
u_clocking	odmb_clocking <Entity odmb_clocking>
vme_buf	iobuf
prom_data_buf	iobuf
ob_dcfeb_tms	obufds
ob_dcfeb_tdi	obufds
ob_dcfeb_injpls	obufds
ob_dcfeb_extpls	obufds
ob_dcfeb_resync	obufds
ob_dcfeb_bc0	obufds
ob_dcfeb_l1a	obufds
ob_dcfeb_tck	obufds
ib_dcfeb_tdo	ibufds
ob_dcfeb_l1a_match	obufds
fd_ccbbx0	fd
resetpulse	PULSE2SAME <Entity PULSE2SAME>
fd_resetpulse_q	fd
fd_l1apulse_q	fd
ds_resync	DELAY_SIGNAL <Entity DELAY_SIGNAL>
ds_bc0	DELAY_SIGNAL <Entity DELAY_SIGNAL>
ds_l1a	DELAY_SIGNAL <Entity DELAY_SIGNAL>
ds_l1a_match	DELAY_SIGNAL <Entity DELAY_SIGNAL>
ds_dcfeb_initjtag	DELAY_SIGNAL <Entity DELAY_SIGNAL>
pulse_dcfeb_initjtag	NPULSE2FAST <Entity NPULSE2FAST>
ib_lvmb_sdout	ibufds
lctdly_gtrg	LCTDLY <Entity LCTDLY>
fdcmd	fdc
fddat	fdc
fdother	fdc
fdrsv	fdc
fd_ccb_softrst	fd
fd_fw_reset	fd
fd_opt_reset	fd
c_goddcrc_cnt	COUNT_EDGES <Entity COUNT_EDGES>
c_dvalid_cnt	COUNT_EDGES <Entity COUNT_EDGES>
c_bad_rx_cnt	COUNT_EDGES <Entity COUNT_EDGES>
mbv	ODMB_VME <Entity ODMB_VME>
mbc	ODMB_CTRL <Entity ODMB_CTRL>

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The documentation for this class was generated from the following files:

• /homes/oshiro/odmb/firmware/odmb7_ucsb_dev/source/odmb7_dev_top.vhd