COUNT_EDGES Entity Reference

Inheritance diagram for COUNT_EDGES:

Entities
COUNT_EDGES_ARCH	architecture

Libraries
ieee
unisim

Use Clauses
ieee.std_logic_1164.all
IEEE.std_logic_unsigned.all
ieee.numeric_std.all
unisim.vcomponents.all

Generics
WIDTH	integer := 16

Ports
COUNT	out std_logic_vector ( WIDTH - 1 downto 0 )
CLK	in std_logic
RST	in std_logic
DIN	in std_logic

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The documentation for this class was generated from the following file:

• /homes/oshiro/odmb/firmware/odmb7_ucsb_dev/source/utils/count_edges.vhd