DELAY_SIGNAL Entity Reference

Inheritance diagram for DELAY_SIGNAL:

Entities
DELAY_SIGNAL_Arch	architecture

Libraries
ieee
unisim

Use Clauses
ieee.std_logic_1164.all
ieee.numeric_std.all
unisim.vcomponents.all

Generics
NCYCLES_MAX	integer := 63

Ports
DOUT	out std_logic
CLK	in std_logic
NCYCLES	in integer range 0 to NCYCLES_MAX
DIN	in std_logic

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The documentation for this class was generated from the following file:

• /homes/oshiro/odmb/firmware/odmb7_ucsb_dev/source/utils/delay_signal.vhd