LCTDLY Entity Reference

Inheritance diagram for LCTDLY:

Entities
LCTDLY_Arch	architecture

Libraries
ieee
work
unisim

Use Clauses
ieee.std_logic_1164.all
unisim.vcomponents.all

Ports
DOUT	out std_logic
CLK	in std_logic
DELAY	in std_logic_vector ( 5 downto 0 )
DIN	in std_logic

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The documentation for this class was generated from the following file:

• /homes/oshiro/odmb/firmware/odmb7_ucsb_dev/source/utils/lctdly.vhd