HEP ASICS
Under Construction
The purpose of this html page is for
sharing information with UCSB
Application-Specific-Integrated-Circuit (ASIC)
Collaboration. This site will be used as an information exchange
during byweekly teleconference meetings.
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NEWS:
Europractice recently hosted a series
of workshops for new customers. One of the most important concepts
stressed at the gathering was the fact that Europractice is a One-Stop
Shop for ASIC customers in that their purpose is to act as a broker
between Customers and; CAD Vendors, Libriaty Vendors, Foundaries,
Packaging Houses and Test Houses. Summary of recent workshops;
Workshop1.pdf Workshop2.pdf
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5X5 Pixel Array Effort
The 5 by 5 pixel array design is meant for mainly
instructional use. The analog and digitial electronics will be designed
using the AMIS 0.35 um CMOS process with foundary services provided by
EuroPractice IC Service in Belgium at www.europractice.com. The typical NMOS and PMOS Structures
will be used in the design. Europractice has provided UCSB a
software design kit dated August 2003 Version 14.0. The design
will make use of a 25 cell array each 250 um square positioned on the
bottom side of a 250 um x 5 = 1.3 mm square chip. If we are unable
to position all of the circuitry under this 250 um square we could go as
large as 400 x 400. For the 250 x 250 pixel the capacitance will be
between 0.5 and 1.0 pf. The pixels are expected to
produce 10k e for each event. This signal will be amplified by a
charge amplifier with a self noise level of 97 e, this is also where the
comparitor thresholds will be set. The shaping time for the analog
pulses will be set at 0.5 us. The comparitor output signals will
be routed to an 18 bit ripple counter.
Simulation Results
TSpice simulations were carried out using
AMIS (typ.) and MOSES models.
Rise and Fall time response for MOSES
Inverter: Invert2.pdf
Rise and Fall time response for AIM035
Inverter:: Invert3.pdf
The rise time was matched to the fall
time for the AIM inverter by increasing the width of the PMos transistor
from 12 to 32 um. :
Invert3a.pdf, The
corresponding netlist used for this analysis is
Netinvert3a.pdf
.
AMIS 035 inverter transfer charactoristics: Aim65inv.pdf
It should be noted that the switching
point for the AIM process is 40% Vdd compared to 46% for the MOSES
process and peak at these input voltages are 60 and 30 uA for the AIM
and MOSES process respectivly.
AMI035 Transmission Gate DC Data: SchematicDC.pdf NetlistDC.pdf SpiceOutputDC.pdf
AMI035 Transmission Gate Pulsed: SchematicPulse.pdf NetlistPulse.pdf SpiceOutPulse.pdf: SpiceOutPulse2.pdf
AMI035 Tri-State Inverter DC Data: SchematicTSI.pdf NetlistTSI.pdf SpiceOutputTSI.pdf 12/1/03
AMI035 Tri-State Inverter Pulsed: SchamticTSIP.pdf NetlistTSIP.pdf SpiceOutputTSIP.pdf SpiceOutTSIPb.pdf 12/1/03
AMI035
Tri-State Inverter Gated and Pulsed: SchematicTSIGP.pdf NetlistTSIGP.pdf SpiceOutTSIGP.pdf 12/1/03
NEW First Inverter Ring Oscillator: LayoutINV1.pdf RingOscNL2.pdf SpiceRingOsc2.pdf
NEW Revised
DFFR: SchematicDFFR.pdf DFFRnet.pdf DFFRpulse.pdf DFFRtd.pdf
NEW
SPDT Transmission Gate : LayoutSPDT1.pdf SpDTSch1.pdf SPDT1nl.pdf SpiceSPDT1.pdf Resistance.pdf
Input Amplifier Noise Calculations
The noise level of the pixel
amplifier was calculated during the early November telephone meeting.
The calculation results show an Equvalent Noise Charge of 97 electrons
with a shaping time of 500 ns and a total input capacitance of 2
pf. The spread sheet is ENC.xls
.
Pixel Readout
The pixel array readout will be
accounplished by placing date from each of the 25 ea 18 bit counters
into a shift register at a 130 mhz rate. Some design work was
carried out while at Oslo on this task. Oslo1.pdf
Current Draw Calculations
The currents for the analog
and digital circuitry is limiited by the ability to move heat off of the
integrated circuit bulk. The current limit for dissipation is 1.0
watt/cm^2. The calculation results point to under 200 uA per pixel
footprint, for a 250 x 250 um pixel. The spread sheet calculation
is Heat1.xls . Based on these calculations it was decided that 50
uA per analog stage would be a reasonable goal.
Descriminator (Comparitor) Notes
T he descriminator design should follow the recent
archetecture used by Paul O'Conner, Wladek Dakrowski and Jan Kaplon
found in recent publications from CERN, Fermi Lab and Rutherford Lab
Libraries. It was decided that the voltage reference input to the
comparitor would be from an external source rather than the 5 bit A/D
Converter as previously dicsussed.
Tanner Tools
UCSB currently is using Tanner L-Edit Pro 10 Version 10.20
which includes T-Spice Pro Verion 9.02, with the schematic capture tool
S Edit Win32 8.10. The web site is at www.tannereda.com. The
tanner tool package is set up for network licensing through
pi0.physics.ucsb.edu 128.111.19.54 at C:\Tanner2\License\
. The PI0 firewall has been set for access to this
license server.
TV Conference Room
The current collaboration will be discussing progress for
the current effort at a regular time in the HEP Video Conference
Room Tel: (805) 893-7569. Our next meeting
will be at 10 AM Pacific Time on Wednesday 4 May . Recently
Einar has been able to see us on the TV monitor.
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Telephone Meeting Summaries
7 January Notes:
- The Inverter cell (See INV1.pdf above) has no
substrate connections for the N Channel FET, this connection
should be seperate from the ground metal1 strip at the bottom of the
cell. The final chip will have three seperate grounds and a
susbtate contact coming off of the chip. GND1: Preamp ground, GND2:
Comparitor ground, GND3: Digital ground and SUB: Substrate. These
will be interconnected outside the chip.
- This has been added below
the GND2 connection on the cell, refer to INV1 layout above.
- The connection to Poly1 with the Via1 may not
be valid, it may not be acceptable to have a contact under a via.
- The Metal1 connection between the source of
the pmos and the drain of the nmos transistors should be the same width
as the metal2 to prevent the "T" Dog-Bone structure at the output
connection.
- The Metal2 width at the
output connection is now all 0.7um wide.
- The NWell can extend to the edge of the cell
so that the wells will interconnect when set side to side.
- The NWell has been
extended over to the sides of the cell, the cell width is now only 4.5um
wide.
- The contact and vias should be set up with
Metal1 and Active as standard cells, call these cells
Contact-Metal-Deposition (CMD), Contact-Metal-P+ (CMP) and
Via1-Metal1-Metal2 (CMM). They can be used to speed cell design.
- Not sure how to save these
with LEdit, as a new layout ie CMD.tdb or as a new cell ? The file
structure is not clear to me with regard to building cells or layouts.
- The simulation of the transmission gate (ASIC
Progress3.ppt) does not look valid, it should be checked and
repeated. The Rs=2k @ 0 v, 3k @ 1.5 v and 2k again at 3 v.
Check for the correct pmos channel width.
- The timing problem with the D FlipFlop
simulation is related to the AD (Area of the Drain0 and PD
(Perimiter of the Drain) entries in the net list, delete AS and PS.
The correct values should be AD=1pm^2 rather than 60pm^2 and
PD=4um rather than 24um as simulated, this will have a major effect on
the speeds. Make the required corrections and run the Spice
simulation again.
- Modified the net list
based on the measured area of the drain (AD=1um * 1um = 1pm^2) and the
perimeter of the drain (PD=1um+1um+0.75um+0.75um=3.5um). The
transistor net list description which I had been using was ; M1 OUT IN
Gnd Gnd EN3 L=0.35u W=0.8u AD=66p PD=24u AS=66p PS=24u
this was changed to M1 OUT IN Gnd Gend EN3 L=0.35u W=0.8 AD=1 PD=4
, AS and PS were removed, the ring oscillator delay times
were reduced from Thl/Tlh 732/589ps to 93/62ps, see above
SpiceRingOsc2.pdf.
- Modified the net list for
the DFFR and measured a Transmission Delay of Td=588ps, see pdf
files above.
- Use 3.3 volts in the simulaiton rather than
3.0v.
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Power-Point Status Reports:
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Tanner Design Kit 2 Ver 3.0 AMIS_cmos035_v3.0.zip
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ASIC Class
Sam and Sean will give informal presentations on a
weekly basis so as to challenge each other to move ahead with the 5x5
pixel array design process. The classes will take place in the 5th floor
TV Conference Room at 3PM every Wednesday, they should last for less
than an hour.
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(Last update on 7/21/2004 by SB)
(Last update on _________ by SM)
Questions? sburke@hep.ucsb.edu