Under Construction, NOTICE: Material on this page is now out of date, refer to the CDMS2 RTF Trigger page  at for the latest informaion. spb

The current CDMS system at Stanford uses a Trigger Logic Board to process all of the sensor triggers and form a Global trigger. This board is documented in the schematic (call me for password at 805 893-7835) of 23OCT98 developed by D Seitz of UCB. The Input/Output scheme is listed below for reference followed by a preliminary discussion related to the second generation system trigger boards  which are currently in the concept stages of design.



From Backplane:

From Front Panel: OUTPUTS:

From Front Panel:



For the CDMS2 system the functionality of the CDMS1 Trigger Logic Board will be replaced with 7 ea Trigger Conditioners which feed their strectched triggers to the Trigger Logic Board. Triggers are generated in the RTF boards which receive analog signals from the charge and phonon tower sensors, typical signals are illustrated in the MathCAD file of  The interface between the TC's and the TL boards is illustrated in the postcript file TrigSys5.eps.  or  trigsys5.pdf.  The function of each is described below with recent updated features highlighted and in italic;


The Trigger Conditioner Board functions to collect tower sensor triggers generated from up to 6 RTF and 3 Wisptrig1.html boards and stretch them to 1us prior to sending them on to Scalars, Time stampers, and the Trigger Logic Boards. The board is in a hybrid 9U VXI FermiLab configuration, as illustrated in the front panel drawing of trigcondpnl.pdf. The board logic is implemented using three Xilinx 84 pin (XC4005XL) PLCC FPGA's.  Each FPGA processes 10 seperate triggers, each of the logic cells are described in Trigger inputs route from a 50 pin D connector at the P1 position on the hybrid backplane. Shaped signals are sent out to; a commercial time stamp card and the Trigger Logic Boards through connectors on the front panel. The preliminary schematic is now available for review at trigcondleft.eps .





The Trigger Logic Boards function to accept qualified stretched inputs from seven TC boards and generate a Global Trigger along with a trigger mask. The TrigLogic4.epsis in X 3 panel-width RTF 9U-configuration and uses four  Xilinx 84 pin (XC4010XL) PLCC FPGA's along with some high-speed 74HS CMOS glue logic. Trigger inputs route from front panel BNC connectors with the stretched triggers routing through seven each 2x32 pin SCSI connectors on the front panel. The veto signal connects to the system through a panel mounted lemo connector since it is NIM logic. The global trigger is available on the backplane and through a BNC connector on the front panel, the Trigger Output pattern is available on three100  pin HIPPI connectors on the front panel with each accomodating 90 bits to commercial Digital I/O Boards, the third connector only carries 34 signals consisting of the last Tower triggers, veto and  random triggers. The board is made up of 84 similar trigger mode selection cells described in the simplified block diagrams of and . The Wisper triggers simply pass through the TLB to the Bit I/O's so that the crate CPU's can determine which sensor signals to capture. The block diagram triglogicblk.eps shows the seven seperate trigger processor  fpga's which form Tower Triggers that are combined to form the grand trigger. The trigger processor fpga incorporates the following logic macros; which uses,,,,, and A preliminary schematic showing one of the fpga sections is shown as




1. Wisper triggers will use RTF Crate slots 7-9 and 12-14 back plane connections (2ea/slot).

2. Questions and answers related to Trigger Logic I/O

3. SCSI -- Small Computer Systems Interface

4. HIPPI -- HIgh Performance Parallel Interface

5. See question 4 for random trigger discussion.

6. See questions 2 and 5 for trigger-enable discussion.

7. See question 8 for ISR Trigger discussion.

8. See question 3 for Real and Live Clock discussion.

9. The Xilinx XC4005XL FPGA's load their programs from a serial PROM as illustrated in the schematic of Testboard1.eps .

10. The Trigger Logic functions use the XC4010XL with all I/O pins used, therefore provision is made to switch between serial PROM hadshaking functions and trigger I/O functions as illustrated in the schematic of Testboard2.eps.

(Last update on 5/24/2000 by SB @ 10:00 AM)