CDMS TRIGGER LOGIC BOARDS

Under Construction, NOTICE: Material on this page is now out of date, refer to the CDMS2 RTF Trigger page  at http://cdms.physics.ucsb.edu/sburke/triglogindex.html for the latest informaion. spb

The current CDMS system at Stanford uses a Trigger Logic Board to process all of the sensor triggers and form a Global trigger. This board is documented in the schematic (call me for password at 805 893-7835) of 23OCT98 developed by D Seitz of UCB. The Input/Output scheme is listed below for reference followed by a preliminary discussion related to the second generation system trigger boards  which are currently in the concept stages of design.

INPUTS:

From Backplane:

9 pairs of Q high and Q low triggers from RTF 5V CMOS          P2 (special)

9 pairs of P high and P low triggers from RTF 5V CMOS           P2 (special)

From Standard VME Buss:

16 VXI Data buss 5V CMOS                                       P1

1 VXI Read 5V CMOS                                                  P1

1 VXI Write 5V CMOS                                                 P1

14 VXI Address buss 5V CMOS                                 P1

1 Random Trigger in 5V CMOS                                 P14 BNC

1 Trig ENA In 5V CMOS                                             P10 BNC

1 Spare Trigger in 5v CMOS                                       P12 BNC

1 ISR Trig in (Logic)                                                     P13 Twinax

1 10 Mhz Clock                                                              P7 BNC

From Front Panel:

1 Real clock out 5V CMOS 50 ohm Rs                         P12 BNC

1 Live clock out 5V CMOS 50 ohm Rs                         P9 BNC

1 Global trigger out 5V CMOS 50 ohm Rs                   P6 BNC

32  Trigger pass-thru's EIA-422                                    P3 2x34  SCSI-2       (HISTBUFF1)

Q1-Q8, P1-P7, Global
14  Trigger pass-thru's EIA-422                                    P5 2x34  SCSI-3      (HISTBUFF2)
Q9, P9, ISR, Rand, Global, Spare

+5v 21 Pins of                P1

Gnd 32 Pins of               P1

For the CDMS2 system the functionality of the CDMS1 Trigger Logic Board will be replaced with 7 ea Trigger Conditioners which feed their strectched triggers to the Trigger Logic Board. Triggers are generated in the RTF boards which receive analog signals from the charge and phonon tower sensors, typical signals are illustrated in the MathCAD file of signals.ps.  The interface between the TC's and the TL boards is illustrated in the postcript file TrigSys5.eps.  or  trigsys5.pdf.  The function of each is described below with recent updated features highlighted and in italic;

TRIGGER CONDITIONERBOARD (TCB):

The Trigger Conditioner Board functions to collect tower sensor triggers generated from up to 6 RTF and 3 Wisptrig1.html boards and stretch them to 1us prior to sending them on to Scalars, Time stampers, and the Trigger Logic Boards. The board is in a hybrid 9U VXI FermiLab configuration, as illustrated in the front panel drawing of trigcondpnl.pdf. The board logic is implemented using three Xilinx 84 pin (XC4005XL) PLCC FPGA's.  Each FPGA processes 10 seperate triggers, each of the logic cells are described in TrigcondC.ps.  Trigger inputs route from a 50 pin D connector at the P1 position on the hybrid backplane. Shaped signals are sent out to; a commercial time stamp card and the Trigger Logic Boards through connectors on the front panel. The preliminary schematic is now available for review at trigcondleft.eps .
 

INPUTS:

From Backplane:

6pairs of Qn high trigger and Qn low trigger (12ea) from RTF 5V CMOS               P2 (special)

6 pairs of Pn high trigger and Pn low trigger (12ea) from RTF 5V CMOS                 P2 (special)

6 Zip Wisper Triggers (6ea) from 3 Trigger Discriminator boards 5V CMOS           P2 (special, Note 1)

UCB HPIB Buss:

16 HPIB/VME Data buss 5V CMOS                                       P1

1 HPIB/VME Read 5V CMOS                                                   P1

1 HPIB/VME Write 5V CMOS                                                  P1

14 HPIB/VME Address buss 5V CMOS                                 P1

From Front Panel:
1 Test Trigger In 5V CMOS                                                      P7

From Front Panel:

30 Stretched Triggers  EIA-422                                   P3 2x34  SCSI-2     (HISTBUFF1)
Q1h-Q6h, P1h-P6h, Q1l-Q6l, P1l-P6l, W1-W6
30 Stretched Triggers  5V CMOS           P3 2x34  SCSI-2     (Trig Logic Bd)
Q1h-Q6h, P1h-P6h, W1-W6, Q1l-Q6l, P1l-P6l

HPIB History buffer mask control over UCB HPIB Buss with readout

REGISTERS:

3 x 16 Bit History buffer control registers as illustrated below;

Q1h,Q1l,P1h,P1l,Wp1,sp,sp,sp,Q2h,Q2l,P2h,P2l,Wp2,sp,sp,sp

Q3h,Q3l,P3h,P3l,Wp3,sp,sp,sp,Q4h,Q4l,P4h,P4l,Wp4,sp,sp,sp

Q5h,Q5l,P5h,P5l,Wp4,sp,sp,sp,Q5h,Q6l,P6h,P6l,Wp6,sp,sp,sp     where sp=spare for not used

(A logical "1" in any of these locations enables the history buffer signal).

TRIGGER LOGIC BOARD (TLB):

The Trigger Logic Boards function to accept qualified stretched inputs from seven TC boards and generate a Global Trigger along with a trigger mask. The TrigLogic4.epsis in X 3 panel-width RTF 9U-configuration and uses four  Xilinx 84 pin (XC4010XL) PLCC FPGA's along with some high-speed 74HS CMOS glue logic. Trigger inputs route from front panel BNC connectors with the stretched triggers routing through seven each 2x32 pin SCSI connectors on the front panel. The veto signal connects to the system through a panel mounted lemo connector since it is NIM logic. The global trigger is available on the backplane and through a BNC connector on the front panel, the Trigger Output pattern is available on three100  pin HIPPI connectors on the front panel with each accomodating 90 bits to commercial Digital I/O Boards, the third connector only carries 34 signals consisting of the last Tower triggers, veto and  random triggers. The board is made up of 84 similar trigger mode selection cells described in the simplified block diagrams of Triglogictimblk.ps and Triglogicglobblk.ps . The Wisper triggers simply pass through the TLB to the Bit I/O's so that the crate CPU's can determine which sensor signals to capture. The block diagram triglogicblk.eps shows the seven seperate trigger processor  fpga's  trigprocsch.ps which form Tower Triggers that are combined to form the grand trigger. The trigger processor fpga incorporates the following logic macros; sqtrigtimer.ps which uses fullshot1.ps, gptimer.ps, gqtimer.ps, sptimer.ps,sqtimer.pswispos1.ps, and tmask.ps.  A preliminary schematic showing one of the fpga sections is shown as triglogicsch1.ps andtriglogicsch2.ps.
INPUTS:

From Backplane:

TBD

Standard VME Buss:

16 VXI Data buss 5V CMOS                                   P1

1 VXI Read 5V CMOS                                              P1

1 VXI Write 5V CMOS                                              P1

14 VXI Address buss 5V CMOS                             P1

From Front Panel:
7X 30 Trigger pass-thru's EIA-422 shld                          P15-21P3 2x34  SCSI-2     (Trig Logic Bd)
Input Triggers A-F: Q1-Q6, P1-P6, W1-W6
1 Random Trigger in 5V CMOS                                 P14 BNC   (Note 5)

1 Trig ENA In 5V CMOS                                             P10 BNC  (Note 6)

1 Spare Trigger in 5v CMOS                                       P12 BNC

1 Pulser Trigger in 5V CMOS                                      P11 BNC

1 ISR Trig in (Logic)                                                      P13 BNC-Twinax (Note 7)

1 10 Mhz Clock                                                               P7 BNC

1 Veto in 5v CMOS NIM                                              P14   lemo

From Front Panel:
 
6 x 7 = 42Trigger Hit Mask's 5V CMOS to Bit I/O    1ea 100 pin ribbon connector       (Bit I/O Bd)
 

3ea Ge Q or P and 3ea Si Q or P = Tower 1

3ea Ge Q or P and 3ea Si Q or P  = Tower 2

3ea Ge Q or P and 3ea Si Q or P  = Tower 3

3ea Ge Q or P and 3ea Si Q or P  = Tower 4

3ea Ge Q or P and 3ea Si Q or P  = Tower 5

3ea Ge Q or P and 3ea Si Q or P  = Tower 6

3ea Ge Q or P and 3ea Si Q or P  = Tower 7
 

1 Veto signal out 5V CMOS                                                      P5 BNC

1 Real time clock 5V CMOS 50 ohm Rs                                   P8 BNC   (Note 8)

1 Live clock out 5V CMOS 50 ohm Rs                                     P9 BNC  (Note 8)

1 Global Trigger out 5V CMOS 50 ohm Rs                              P6 BNC   (to master trigger board)

 Triggers EIA-422                                                                        P5 2x34 SCSI2      (HISTBUFF)

Veto, ISR, Rand, Global Trigger, ON0,ON1,ON2,ON3
To The Backplane:
Global trigger out 5V CMOS                                &nb sp;        P2

REGISTERS:

12ea  2-Bit Mode registers with UCB HPIB Buss

         MODE          Pattern (msb, lsb)

 
OFF               0 0

HI                  0 1

HI * LO         1 0  (Default)

L0                 1 1
 

6ea  2-Bit Mask registers with UCB HPIB Buss
 
     MASK         Pattern (msb, lsb)
 
SET MASK             0 0

Q (charge) or Phonon  0 1 (Default)

Wisper                     1 0

OFF                        1 0

MASK     DETECTOR

0                Ge P or Q

1                Si  P or Q

2                Ge P or Q

3                Si P or Q

4                Ge P or Q

5                Si  P or Q
 

 NOTES:

1. Wisper triggers will use RTF Crate slots 7-9 and 12-14 back plane connections (2ea/slot).

2. Questions and answers related to Trigger Logic I/O

3. SCSI -- Small Computer Systems Interface

4. HIPPI -- HIgh Performance Parallel Interface

5. See question 4 for random trigger discussion.

6. See questions 2 and 5 for trigger-enable discussion.

7. See question 8 for ISR Trigger discussion.

8. See question 3 for Real and Live Clock discussion.

9. The Xilinx XC4005XL FPGA's load their programs from a serial PROM as illustrated in the schematic of Testboard1.eps .

10. The Trigger Logic functions use the XC4010XL with all I/O pins used, therefore provision is made to switch between serial PROM hadshaking functions and trigger I/O functions as illustrated in the schematic of Testboard2.eps.

(Last update on 5/24/2000 by SB @ 10:00 AM)