CDMS DAQ Questions and Answers
Under Construction
1. How is the muon veto implemented in the CDMS1 SUF?
The current veto is done offline. In the software it is decided whether a veto hit has occured close enough in time to the detector event to call it muon-coincident.
2. What is the fast live clock and how is it used?
The fast clock is the output of the 1kzh oscillator gated by the trigger enable and shut off by the global trigger. The live clock provides a 1khz signal during the time that the system is ready and waiting for triggers, it is an indication of the system live time.
3. What is the real clock out and how is it used?
This clock is simply the ungated 1khz clock out. It is used as a scaler input which is comparted to a scaler which uses the fast clock, the ratio of these two counters is the system live fraction.
4. What is the random trigger and how is it used?
The random trigger is a signal generated by the DAQ computer, it is sent out over it's bit I/O, it fires the trigger and is used for collecting empty traces (ie. no event) for calculating noise.
5. What generates trigger enable and how does it cycle?
Trigger enable is generated by the input/output register in the VXI crate which is computer controlled. The computer starts the digitizers and history buffer, waits a set time for the digitizers to record the pretrigger data, then pulls the trigger enable high allowing the Global Trigger D flip flop on the Trigger Logic Board to fire resulting in a Global Trigger.
6. The current generation trigger logic board on CDMS1 has four modes which are set by the VXI controller board via a IEEE488 connection to the DAQ computer, they are; 0:Dissbled, 1:Use high trigger, 2:Use low trigger gated by high and 3:Use low trigger. How are they used?
Mode 3 is used during normal data acquisiton, mode 2 is used for calibration to reduce the trigger rate from high energy gammas. Mode 1 is not used.
7. What is the proposed third below-trigger trigger (Wisp Trigger)and how will it be used?
The extra low trigger Wisp Trigger will trip if we have low level energy in a detector channel even though the low trigger was not set. It could be generated by taking analog signals from the RTF board front panel SMD connectors and sending them to a pair of new multichannel processor boards in each the 9U VXI DAQ crates. The Wisp Trigger boards would employ some analog filtering and descriminator to make the third threshold. The threshold would be set using VXI Controller board. .
8. What is the ISR Trigger?
The ISR trigger is a differential signal that comes from the Front End (FE) rack. The detectors have pulser circuits on them that allow us to generate fake events. A fake event is produced by sending a GPIB trigger signal from the computer to the GPIB control box for the FE rack; this fires a signal off onto the backplane that tells all the detectors' pulser circuits to fire. This trigger signal is then carried back to the RTF rack by the ISR trigger line. We run the ISR trigger signal into the history buffer so we have a record that the event was a fake event that we generated. We don't actually trigger off of it because we want the fake detector traces to generate the trigger themselves (it was planned as a way of measuring trigger efficiency).
9. How do we end of with four triggers from six detector signals?
The six detector signals are amplified in the Front End rack and sent off to the Receiver Trigger Filter (RTF) rack where they are summed into a charge sum and a phonon sum, the sums are then filtered and sent to a pair low level and high descriminators where the Qhi, Qlo, Phi and Plo triggers are generated. All of the lator functions are carried out on the RTF boards.
10. How will the muon veto of the global trigger be accomplished?
Whenever the muon veto fires, we want to generate a gate that prevents the global trigger flip-flop from seeing an edge on its clock input for 5us. The muon veto signal will be connected into a one-shot and AND the Q-bar output of the one-shot with the OR of all of the selected RTF triggers. The random triggers will still be allowed to set the global trigger.
11. How will prescaling be used to allow some events to pass through even though they should be vetoed?
We don't want to let the muon veto blank every event, just some preset fraction of them. So this would require a programmable counter between the muon veto signal input to the board and the 1-shot. The muon veto signal would clock the counter; we could invert the carry-out output and AND it with the muon veto signal before going to the 1-shot so that the veto signal would propagate through and blank triggers except if the carry-out bit went high. This aspect of the design is a moving target. The design will require that the muon veto signal doesn't propagate through before the carry-out has had a chance to blank it.
12. What is the transfer function of the charge and phonon filtering.
Q Low Band: 32 - 32 khz, Tr = 5 us, Gain = 40dB, Negative clipper, +10v limiter
Q Hi Band: 1000 hz - 3 Mhz, Tr = 300 ns, Gain = 1.0
P Low Band: 0.8 hz - 80 hz, Tr=200ms, 2ms, Gain = 46dB, 600mV pp limiter prior to gain stage
P High Band: 1 hz - 50 hz , Tr = 50 ms, Gain = 1.0
13. What is a paddle?
A single piece of scintillator which may have more than one photomultiplier tube (PMT) attached. The plan is to have each PMT associated with a single paddle summed before connection to a descriminator.
14. Where do we come up with 42 PMT's, the veto shield as designed has 36?
Based on input from Dave Hale we will have; 6 ea top + 3 ea on 8 sides + 6 ea bottom = 36, so the 6 extra must be another scintillator shield.
15. What would be the best transfer function for the Wisp Trigger processor?
Since the band limiting has already taken place we can simply use the RTF filtered analog outputs and operate on them with a lower threshold than previously used followed by an OR function to generate the Wisp Trigger for a ZIP.
16. Why is the muon veto needed?
The veto tells us that a cosmic ray muon came by at the same time as a hit in the detectors and thus may have been responsible for the hit as opposed to a dark matter particle which would not set of the veto.
17. What is the reason for measuring the analog pulse heights of the PMT signals?
To keep track of the seperate PMT sensitivities. Signal amplitudes are maintained by adjusting the level of the seperate PMT high voltages. SB
18. What kind of photomultiplier tubes are we using ?
The current system uses RCA 8575's which provide negative going pulses that range from a few mV to volts with rise times of fron 5 to 10 ns. The new system will use Hamamatsu R329-02 PMT's with E4512-501 bases at a cost of $500 + $240, they have peak sensitivity at 400 nm wavelength. SB
19. The Trigger Conditioner and the Trigger Logic boards will emply readback latches so that the setup can be determined thereby eliminating the need to restablish the board configuration if unsure. How will these latches be read out?
RTF UCB Address/Data Buss on P1 which gets converted to HPIB. DB
20. What type of input connectors will the Wisper board use. Inputs come from the SMD connectors on the RTF boards?
SMD connectors may be a good choice; small panel space, other end is SMD. SB It makes sense to use SMD connectors on both ends, it will be spaghetti-like. DB
21. Could we eliminate the need for the Wisper board function at SUDAN by changing all of the High Triggers on the RTF to Wisper Triggers. This concept may have merit for two reasons; a. Low cosmic background at the SUDAN site eliminating the need for the High Trigger and b. Lower System complexity and cost.
The High Triggers are still required for calibration, to suppress events at high energy and keep the trigger rate down. DB
22. Why is the buss on the RTF P1 connector refered to as the HPIB Interface, is it not a standard VXI/VME Buss which is simply employing a HPIB VXI plug-in to talk over the VXI/VME Buss?
This buss does not follow the VXI/VME Buss Spec, it is a hybrid buss set up by Dennis Seitz of Berkeley. The board that controls the data exchange process is the "Detector Electronics 9U Subrack Controller Board" which resides in slot 21 of the RTF rack.
23. What is the function of P3 (2 x 34 pin SCSI-2) on the current RTF Trigger Logic Board front panel?
It appears that it is not used and intended for future use.
24. What are the P3 - P5 connector part numbers as used on the current SUF System?
I am looking at a 2 x 34 pin SCSI-2 AMPLIMITE .050 Series connector AMP PN 787171-7
25. If we use the CAEN VME 32 Channel Pipeline as a Time Stamp with each Trigger Conditioner we will be short 4 channels. What channels will we drop from the mix?
Rather than using two Wisper Triggers for every Detector channel we will use one thereby not coming up short at all but thereby providing two spare Time Stamp inputs for each Tower.
If we use the CAEN unit we will need two per Digitizer Crate rather than one of the VXI Technologies VM1602 which we are currently using at SUF. However even though we would need two of the CAEN Stamps, the added cost may be worth it if we achieve an access time savings.
26. Does the Trigger Conditioner Board (TCB) Mask only control the History Buffer outputs and not the Trigger or Monitor Outputs?
The TCB Mask control does not effect the Trigger or Monitor Outputs. Triggers can be dissabled using the Mode control in each of the Trigger Logic Boards located in the Digitizer Crates. SB
27. What is the plan for the RTF Crate HPIB Controller boards for CDMS-II ?
Additional 9U Controllers will be built by UC Berkley
28. Why is does the 9U Controller board use a 64 pin DIN C Connector rather than the standard IEEE-488 24 pin connector?
This HPIB interface is not a standard.
29. What is the main goal in the veto panel test program at UCSB?
The purpose of testing the new veto counters isn't so much to test the scintillator itself as to test whether the way we put together light guides, scintillator, and PMT's yields a counter with sufficiently uniform response and high enough efficiency for particles passing through. DB
30. Will the new Trigger Conditioner Board have the version and serial numbers hard wired on the board like the RTF board?
Yes, these registers will be mapped just as the RTF board is.
31. What will be the power up status for the trigger pass registers?
All will be enabled on power-up
32. Describe the TCB Digital port mapping with regard to reading out the board numbers and the trigger pass registers.
33. Is it a requirement that the 100 ns time stamp signals from the TCB be synchronized with a 10 Mhz clock as they are in the present SUF Trigger Logic Board?
The specs for the TCB for CDMS2 call for 1000 ns time stamp signals with no special clock synchronizing requirement.
34. I see that the Trigger Logic Board Block Diagram rev B of 22 July 98 does not agree with the schematic of 23 October 98. I assume that I should not use the block diagram for guidance.
The schematic is assumed to be correct.
35.On the Trigger Logic Schematic, are the following notations typo errors or are they as built? 1. Q2HI oneshot U1.8 pulse width indicated as 10 us 2. Q2LO secondary oneshot U2.11 resistor shown as 2.2 kohms 3. P2Hi oneshot U6.9 resistor shown as 158 khoms
36. What are the reasons for the oneshot pulse widths used on the current SUF Trigger Logic Board? The current oneshot pulse widths used on the SUF Trigger Logic Board are listed below; 1. QHI 5ms 2. QLO 5us and 1us 3. PHI 10ms 4. PLO 5ms and 1ms?
37. What onshot times should be used for the extra low triggers?
For the extra low triggers I will use 2x the times that are currently used for PHI and PLO sutch that; 5. QXL 20ms 6. PXL 10ms and 2ms
NOTES:
1. Veto panels will be tested at UCSB High Bay Clean Room.
(Last update on 5/19/1999 by SB @ 12:00 AM)
Questions or Comments ? sburke@hep.ucsb.edu