CDMS Wisper Trigger Board

Under Construction

The Wisper Trigger Board (WTB) functions to establish weather or not any low level detector data exists at the time of a global trigger even though none of the detectors low level triggers were set. The board is in a hybrid 9U VXI FermiLab configuration. High level input signals are passed from front panel connectors to descriminators following a stage of band pass filtering. The descriminator thresholds are set under the control of HPIB Controller Board. The logic is high speed 74HS CMOS. Trigger outputs route to the 50 pin D connector at the P1 position on the hybrid backplane.

From Backplane:

TBD

Standard VME Buss:
 

16 VXI Data buss 5V CMOS                                        P1

1 VXI Read 5V CMOS                                                   P1

1 VXI Write 5V CMOS                                                  P1

14 VXI Address buss 5V CMOS                                 P1
 

From Front Panel:
 
Two sets of Filtered Analog Charge and Phonon signals        P4 -P11 SMD or BNC
 P1L, P1H, Q1L, Q1H, P2L, P2H, Q2L, Q2H

From Front Panel:
2 Wisp Triggers   5V Line Driver                        P16 - P17 SMD
From Backplane:
2 Wisp Triggers    5V CMOS                               P2 (special) Note 1

2 Wisp Trigger LED's                                                  W1, W2 (Note 2)

1 VME Select LED

1 CLEAR Button

2 Threshold levels 16 bit registers with 12 bits of data

 

NOTES:

1. Fermilab P2 50 pin backplane pins, RTF Slots 7,8,9,18,19 & 20. (See Trig. Distribution Pinout Rev. A)

2. latched