Processes
cfg_reg_proc	( RST , CLK , cfg_reg_we , cfg_reg_in , cfg_regs )
const_reg_proc	( RST , CLK , const_reg_we , const_reg_in , const_regs )

Constants
FW_VERSION	std_logic_vector ( 15 downto 0 ) := x " D3B7 "
FW_ID	std_logic_vector ( 15 downto 0 ) := x " D3B7 "
FW_MONTH_DAY	std_logic_vector ( 15 downto 0 ) := x " 1021 "
FW_YEAR	std_logic_vector ( 15 downto 0 ) := x " 2021 "
able_write_const	std_logic := ' 0 '
cfg_reg_mask_we	std_logic_vector ( 15 downto 0 ) := x " FDFF "
const_reg_mask_we	std_logic_vector ( 15 downto 0 ) := x " FFE1 "
cfg_reg_init	cfg_regs_array := ( x " 5468 " , x " 6973 " , x " 2069 " , x " 7320 " , x " 6120 " , x " 7465 " , x " 7374 " , x " 2066 " , x " 6F72 " , x " 2077 " , x " 7269 " , x " 7469 " , x " 6E67 " , x " 2050 " , x " 524F " , x " 4D21 " )
const_reg_init	cfg_regs_array := ( x " 0D3B " , FW_VERSION , FW_ID , FW_MONTH_DAY , FW_YEAR , x " FFF5 " , x " FFF6 " , x " FFF7 " , x " FFF8 " , x " FFF9 " , x " FFFA " , x " FFFB " , x " FFFC " , x " FFFD " , x " FFFE " , x " FFFF " )
cfg_reg_mask	cfg_regs_array := ( x " 003f " , x " 003f " , x " 0001 " , x " 003f " , x " 001f " , x " 001f " , x " 000f " , x " 01ff " , x " 00ff " , x " ffff " , x " ffff " , x " 0fff " , x " ffff " , x " ffff " , x " ffff " , x " ffff " )

Types
rh_reg	is array ( 2 downto 0 ) of std_logic_vector ( 15 downto 0 )
rh_reg_array	is array ( 0 to NREGS ) of rh_reg

Signals
do_cfg	std_logic := ' 0 '
do_const	std_logic := ' 0 '
do_cfg_we	std_logic := ' 0 '
do_const_we	std_logic := ' 0 '
do_cfg_we_q	std_logic := ' 0 '
do_const_we_q	std_logic := ' 0 '
bit_const	std_logic := ' 0 '
cfg_reg_triple	rh_reg_array
cfg_regs	cfg_regs_array
cfg_reg_we	integer range 0 to NREGS
cfg_reg_index	integer range 0 to NREGS
vme_cfg_reg_we	integer range 0 to NREGS
cfg_reg_in	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
const_reg_triple	rh_reg_array
const_regs	cfg_regs_array
const_reg_index	integer range 0 to NCONST
const_reg_index_p1	integer range 0 to NCONST
const_reg_we	integer range 0 to NREGS
vme_const_reg_we	integer range 0 to NREGS
const_reg_in	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
cmddev	std_logic_vector ( 15 downto 0 )
dd_dtack	std_logic := ' 0 '
d_dtack	std_logic := ' 0 '
q_dtack	std_logic := ' 0 '
ce_d_dtack	std_logic := ' 0 '
w_mask_vme	std_logic
r_mask_vme	std_logic
mask_vme	std_logic_vector ( NCONST downto 0 ) := ( others = > ' 0 ' )

The documentation for this class was generated from the following files:

Processes

Constants