VMEMON_Arch Architecture Reference

Signals
cmddev	std_logic_vector ( 15 downto 0 )
w_odmb_rst	std_logic := ' 0 '
w_dcfeb_reprog	std_logic := ' 0 '
w_dcfeb_resync	std_logic := ' 0 '
w_opt_rst	std_logic := ' 0 '
reprog	std_logic := ' 0 '
out_odmb_cal	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
w_odmb_cal	std_logic := ' 0 '
r_odmb_cal	std_logic := ' 0 '
odmb_cal_inner	std_logic := ' 0 '
out_tp_sel	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
tp_sel_inner	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
w_tp_sel	std_logic := ' 0 '
r_tp_sel	std_logic := ' 0 '
out_max_words_dcfeb	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
max_words_dcfeb_inner	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
w_max_words_dcfeb	std_logic := ' 0 '
r_max_words_dcfeb	std_logic := ' 0 '
out_loopback	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
loopback_inner	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
w_loopback	std_logic := ' 0 '
r_loopback	std_logic := ' 0 '
out_txdiffctrl	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
txdiffctrl_inner	std_logic_vector ( 3 downto 0 )
r_txdiffctrl	std_logic := ' 0 '
out_dcfeb_done	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
r_dcfeb_done	std_logic := ' 0 '
out_mux_data_path	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
w_mux_data_path	std_logic := ' 0 '
r_mux_data_path	std_logic := ' 0 '
mux_data_path_inner	std_logic := ' 0 '
out_mux_trigger	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
w_mux_trigger	std_logic := ' 0 '
r_mux_trigger	std_logic := ' 0 '
mux_trigger_inner	std_logic := ' 0 '
out_mux_lvmb	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
w_mux_lvmb	std_logic := ' 0 '
r_mux_lvmb	std_logic := ' 0 '
mux_lvmb_inner	std_logic := ' 0 '
out_odmb_ped	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
w_odmb_ped	std_logic := ' 0 '
r_odmb_ped	std_logic := ' 0 '
odmb_ped_inner	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
out_test_ped	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
w_test_ped	std_logic := ' 0 '
r_test_ped	std_logic := ' 0 '
test_ped_inner	std_logic := ' 0 '
out_mask_pls	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
mask_pls_inner	std_logic := ' 0 '
w_mask_pls	std_logic := ' 0 '
r_mask_pls	std_logic := ' 0 '
out_mask_l1a	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
mask_l1a_inner	std_logic_vector ( NCFEB downto 0 ) := ( others = > ' 0 ' )
w_mask_l1a	std_logic := ' 0 '
r_mask_l1a	std_logic := ' 0 '
r_odmb_data	std_logic
w_dcfeb_pulse	std_logic := ' 0 '
dcfeb_pulse	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
ce_d_dtack	std_logic
d_dtack	std_logic
q_dtack	std_logic

Instantiations
pls_fwreset	PULSE2FAST <Entity PULSE2FAST>
pls_optreset	PULSE2FAST <Entity PULSE2FAST>
pls_l1areset	PULSE2FAST <Entity PULSE2FAST>
pls_reprog	NPULSE2SAME <Entity NPULSE2SAME>
fd_testcal	fdce
fd_w_tp_sel	fdce
fd_w_max_words_dcfeb0	fdce
fd_w_max_words_dcfeb11	fdce
fd_w_max_words_dcfeb10	fdpe
fd_w_loopback	fdce
fd_muxdatapathsel	fdce
fd_muxtriggersel	fdce
fd_muxlvmbsel	fdce
fd_odmbped1	fdce
fd_odmbped2	fdce
fd_testped	fdce
fd_w_mask_pls	fdce
fd_w_mask_l1a	fdce
pulse_inj	NPULSE2SAME <Entity NPULSE2SAME>
pulse_pls	NPULSE2SAME <Entity NPULSE2SAME>
pulse_l1a	PULSE2FAST <Entity PULSE2FAST>
pulse_lct	PULSE2FAST <Entity PULSE2FAST>
pulse_ext	PULSE2FAST <Entity PULSE2FAST>
pulse_bc0	PULSE2FAST <Entity PULSE2FAST>
fd_d_dtack	fdce
fd_q_dtack	fd

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The documentation for this class was generated from the following file:

• /homes/oshiro/odmb/firmware/odmb7_ucsb_dev/source/odmb_vme/vmemon.vhd