SYSTEM_MON_ARCH Architecture Reference

Processes
PROCESS_2	( SLOWCLK )

Components
oneshot	<Entity oneshot>
voltage_mon	<Entity voltage_mon>
ila_volMon

Types
t_csstates	is ( S_CS_IDLE , S_CS_SET )
t_vmondata_arr	is array ( integer range<> ) of std_logic_vector ( 11 downto 0 )

Signals
sysmon_daddr	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
sysmon_dout	std_logic_vector ( 15 downto 0 )
sysmon_drdy	std_logic
sysmon_den	std_logic := ' 0 '
sysmon_alm	std_logic_vector ( 15 downto 0 )
q_strobe	std_logic
q2_strobe	std_logic
csstate	t_csstates := S_CS_IDLE
adc_cs_inner	std_logic_vector ( 4 downto 0 )
adc_din_inner	std_logic
cs_inner	std_logic
din_inner	std_logic
clk_inner	std_logic
chip_selected	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
cmddev	std_logic_vector ( 15 downto 0 )
r_sys_mon	std_logic := ' 0 '
w_vol_mon	std_logic := ' 0 '
r_vol_mon	std_logic := ' 0 '
which_chip	std_logic_vector ( 3 downto 0 )
which_chan	std_logic_vector ( 3 downto 0 )
which_chip_inner	std_logic_vector ( 3 downto 0 )
which_chan_inner	std_logic_vector ( 3 downto 0 )
vmon_dout_chan	t_vmondata_arr ( 7 downto 0 )
vmon_dout	std_logic_vector ( 11 downto 0 ) := x " 000 "
vmon_dout_valid	std_logic := ' 0 '
vmon_chanidx	integer range - 1 to 6 := 0
vmon_chipidx	integer range - 1 to 6 := 0
vmon_n_valid	integer := 0
startchannelvalid	std_logic := ' 0 '
startchannelvalid2	std_logic := ' 0 '
data_done	std_logic := ' 0 '
ctrlseqdone	std_logic := ' 0 '
data_valid_cntr	std_logic_vector ( 7 downto 0 ) := x " 00 "
current_channel	std_logic_vector ( 2 downto 0 ) := " 000 "
dd_dtack	std_logic
d_dtack	std_logic
q_dtack	std_logic
outdata_inner	std_logic_vector ( 15 downto 0 )
variousflags	std_logic_vector ( 15 downto 0 ) := x " 0000 "
ila_trigger	std_logic_vector ( 7 downto 0 ) := x " 00 "
ila_adc	std_logic_vector ( 7 downto 0 )

Instantiations
u1_oneshot	oneshot <Entity oneshot>
u2_oneshot	oneshot <Entity oneshot>
which_chip_inner_gen_i	fdce
which_chan_inner_gen_i	fdce
cs_gen_i	fdpe_1
din_gen_i	fdce
u_voltagemon	voltage_mon <Entity voltage_mon>
sysmone1_inst	sysmone1
fd_strobe	fd
fd_strobe2	fd
fd_d_dtack	fdc
fd_q_dtack	fd
i_ila	ila_volmon

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The documentation for this class was generated from the following files:

• /homes/oshiro/odmb/firmware/odmb7_ucsb_dev/source/odmb_vme/system_mon.vhd