SPI_CTRL_Arch Architecture Reference

Processes
PROCESS_3	( cmd_fifo_out )
enable_cmd_fifo_fsm	( CLK40 , RST )
process_cmd_fifo_fsm	( CLK40 , RST )
timer_fst	( CLK40 , RST )
status_fsm	( CLK40 , RST )
process_nword_readback	( CLK40 , RST )
process_nword_readback_slow	( CLK2P5 )

Components
spi_interface	<Entity spi_interface>
spi_cmd_fifo
spi_readback_fifo
ila_spi

Constants
custom_enable	std_logic := ' 1 '

Types
cmd_fifo_states	is ( S_IDLE , S_LOAD_ADDR_CMD , S_LOAD_ADDR_STALL_1 , S_LOAD_ADDR_STALL_2 , S_LOAD_ADDR_LOWER , S_READ_CMD , S_READ_LOW , S_READ_WAIT , S_READ_REGISTER_CMD , S_READ_REGISTER_LOW , S_READ_REGISTER_WAIT , S_READ_ID_CMD , S_READ_ID_LOW , S_READ_ID_WAIT , S_CLEAR_STATUS_CMD , S_CLEAR_STATUS_LOW , S_CLEAR_STATUS_WAIT , S_WRITE_CMD , S_WRITE_STALL_1 , S_WRITE_STALL_2 , S_WRITE_WORD , S_WRITE_START , S_WRITE_WAIT , S_CUSTOM_CMD , S_CUSTOM_NREAD_STALL , S_CUSTOM_NREAD , S_CUSTOM_WORD_STALL , S_CUSTOM_WORD , S_CUSTOM_START_STALL , S_CUSTOM_START , S_CUSTOM_WAIT , S_ERASE_CMD , S_ERASE_LOW , S_ERASE_WAIT , S_LOCK_CMD , S_LOCK_LOW , S_LOCK_WAIT , S_UNLOCK_CMD , S_UNLOCK_LOW , S_UNLOCK_WAIT , S_READ_LOCK_CMD , S_READ_LOCK_LOW , S_READ_LOCK_WAIT , S_WRITE_REGISTER_CMD , S_WRITE_REGISTER_STALL_1 , S_WRITE_REGISTER_STALL_2 , S_WRITE_REGISTER_LOWER , S_WRITE_REGISTER_WAIT , S_START_TIMER_CMD , S_STOP_TIMER_CMD , S_RESET_TIMER_CMD , S_RESET_STATUS_CMD , S_SWITCH_PROM_CMD , S_UNKNOWN_CMD , S_STALL )
rd_fifo_states	is ( S_FIFOIDLE , S_FIFOWRITE_PRE , S_FIFOWRITE )

Signals
cmd_fifo_empty	std_logic := ' 1 '
cmd_fifo_full	std_logic := ' 0 '
cmd_fifo_read_en	std_logic := ' 0 '
cmd_fifo_out	std_logic_vector ( 15 downto 0 ) := x " 0000 "
prom_addr	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
prom_load_addr	std_logic := ' 0 '
temp_pagecount	std_logic_vector ( 17 downto 0 ) := x " 0000 " & " 01 "
temp_sectorcount	std_logic_vector ( 13 downto 0 ) := x " 000 " & " 01 "
temp_cmdindex	std_logic_vector ( 3 downto 0 ) := x " 4 "
read_nwords	unsigned ( 11 downto 0 ) := ( others = > ' 0 ' )
cmd_fifo_state	cmd_fifo_states := S_IDLE
write_word_counter	unsigned ( 11 downto 0 ) := ( others = > ' 0 ' )
cmd_fifo_out_upper_mone	unsigned ( 10 downto 0 ) := ( others = > ' 0 ' )
program_nwords	unsigned ( 11 downto 0 ) := ( others = > ' 0 ' )
write_fifo_write_en	std_logic := ' 0 '
prom_read_en	std_logic := ' 0 '
prom_erase_en	std_logic := ' 0 '
prom_write_en	std_logic := ' 0 '
prom_unlock_en	std_logic := ' 0 '
prom_lock_en	std_logic_vector ( 1 downto 0 ) := " 00 "
prom_read_lock_en	std_logic_vector ( 1 downto 0 ) := " 00 "
prom_read_id_en	std_logic := ' 0 '
clear_status_en	std_logic := ' 0 '
prom_wr_register_en	std_logic_vector ( 3 downto 0 ) := x " 0 "
read_done	std_logic := ' 0 '
erase_done	std_logic := ' 0 '
write_done	std_logic := ' 0 '
lock_done	std_logic := ' 0 '
read_lock_done	std_logic := ' 0 '
unlock_done	std_logic := ' 0 '
write_register_done	std_logic := ' 0 '
read_register_en	std_logic_vector ( 3 downto 0 ) := x " 0 "
read_register_done	std_logic := ' 0 '
read_id_done	std_logic := ' 0 '
clear_status_done	std_logic := ' 0 '
spi_timer_en	std_logic := ' 0 '
spi_timer_rst	std_logic := ' 0 '
spi_status_rst	std_logic := ' 0 '
register_contents	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
prom_custom_en	std_logic_vector ( 11 downto 0 ) := x " 000 "
prom_custom_rdwords	std_logic_vector ( 15 downto 0 ) := x " 0000 "
custom_done	std_logic := ' 0 '
fsm_is_enabled	std_logic := ' 1 '
rd_fifo_state	rd_fifo_states := S_FIFOIDLE
wr_dvalid_cnt	unsigned ( 31 downto 0 ) := x " 00000000 "
load_rd_fifo	std_logic := ' 0 '
readback_fifo_wr_en	std_logic := ' 0 '
start_read_fifo_q	std_logic := ' 0 '
readback_fifo_rd_en	std_logic := ' 0 '
rd_data_valid	std_logic := ' 0 '
spi_readdata	std_logic_vector ( 15 downto 0 ) := x " 0000 "
readback_fifo_wr_rst_busy	std_logic := ' 0 '
readback_fifo_rd_rst_busy	std_logic := ' 0 '
nwords_readback	unsigned ( 10 downto 0 ) := " 00000000000 "
read_slowclk_toggle	std_logic := ' 0 '
read_slowclk_toggle_meta	std_logic := ' 0 '
read_slowclk_toggle_sync1	std_logic := ' 0 '
read_slowclk_toggle_sync2	std_logic := ' 0 '
read_en_clk40_pulse	std_logic := ' 0 '
readback_fifo_full	std_logic := ' 0 '
readback_fifo_empty	std_logic := ' 0 '
spi_timer_inner	unsigned ( 31 downto 0 ) := x " 00000000 "
spi_register_inner	std_logic_vector ( 15 downto 0 ) := x " 0000 "
spi_register_we	std_logic := ' 0 '
spi_register_readback	std_logic_vector ( 7 downto 0 ) := x " 00 "
spi_timer_countup	unsigned ( 7 downto 0 ) := x " FF "
readback_fifo_empty_meta	std_logic := ' 0 '
readback_fifo_empty_sync	std_logic := ' 0 '
readback_fifo_full_meta	std_logic := ' 0 '
readback_fifo_full_sync	std_logic := ' 0 '
cmd_fifo_empty_meta	std_logic := ' 0 '
cmd_fifo_empty_sync	std_logic := ' 0 '
cmd_fifo_full_meta	std_logic := ' 0 '
cmd_fifo_full_sync	std_logic := ' 0 '
cmd_fifo_read_en_q	std_logic := ' 0 '
cmd_fifo_read_en_pulse	std_logic := ' 0 '
ila_probe	std_logic_vector ( 511 downto 0 ) := ( others = > ' 0 ' )
prom_cs2_b_inner	std_logic := ' 0 '
cnfg_data_in_inner	std_logic_vector ( 7 downto 4 ) := ( others = > ' 0 ' )
cnfg_data_out_inner	std_logic_vector ( 7 downto 4 ) := ( others = > ' 0 ' )
cnfg_data_dir_inner	std_logic_vector ( 7 downto 4 ) := ( others = > ' 0 ' )
prom_select	std_logic := ' 0 '

Instantiations
ila_spi_i	ila_spi
spi_cmd_fifo_i	spi_cmd_fifo
spi_readback_fifo_i	spi_readback_fifo
spi_interface_inst	spi_interface <Entity spi_interface>

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The documentation for this class was generated from the following files:

• /homes/oshiro/odmb/firmware/odmb7_ucsb_dev/source/spi/spi_ctrl.vhd