CALIBTRG_arch Architecture Reference

Components
LCTDLY	<Entity LCTDLY>

Signals
bc0_cmd	std_logic
bc0_rst	std_logic
bc0_inner	std_logic
start_trg_cmd	std_logic
start_trg_rst	std_logic
start_trg_inner	std_logic
stop_trg_cmd	std_logic
stop_trg_rst	std_logic
stop_trg_inner	std_logic
l1asrst_cmd	std_logic
l1asrst_rst	std_logic
l1asrst_clk_cmd	std_logic
l1asrst_cnt_rst	std_logic
l1asrst_cnt_ceo	std_logic
l1asrst_inner	std_logic
l1asrst_cnt	std_logic_vector ( 15 downto 0 )
ttccal_cmd	std_logic_vector ( 2 downto 0 )
ttccal_rst	std_logic_vector ( 2 downto 0 )
ttccal_inner	std_logic_vector ( 2 downto 0 )
ccbinjin_1	std_logic
ccbinjin_2	std_logic
ccbinjin_3	std_logic
ccbplsin_1	std_logic
ccbplsin_2	std_logic
ccbplsin_3	std_logic
plsinjen_1	std_logic
plsinjen_rst	std_logic
plsinjen_inv	std_logic
bx0_1	std_logic
bxrst_1	std_logic
clken_1	std_logic
l1arst_1	std_logic
logich	std_logic := ' 1 '
logich4	std_logic_vector ( 3 downto 0 ) := " 1111 "
logic5	std_logic_vector ( 3 downto 0 ) := " 0101 "
finj_inv	std_logic
preinj_1	std_logic
preinj	std_logic
fpls_inv	std_logic
prepls_1	std_logic
prepls	std_logic
inj_cmd	std_logic
inj_1	std_logic
inj_2	std_logic
inj_3	std_logic
inj_4	std_logic
inj_5_a	std_logic
inj_5_b	std_logic
inj_inner	std_logic
inj_cnt	std_logic_vector ( 15 downto 0 )
pls_cmd	std_logic
pls_1	std_logic
pls_2	std_logic
pls_3	std_logic
pls_4	std_logic
pls_5_a	std_logic
pls_5_b	std_logic
pls_inner	std_logic
pls_cnt	std_logic_vector ( 15 downto 0 )
pedestal_inv	std_logic
rstpls_cmd	std_logic
rstpls	std_logic
rstpls_cnt_ceo	std_logic
rstpls_cnt_tc	std_logic
rstpls_1	std_logic
rstpls_cnt	std_logic_vector ( 7 downto 0 )
injpls_cmd	std_logic
injpls_rst	std_logic
injpls_1	std_logic
injpls_inner	std_logic
cal_gtrg_cmd	std_logic
cal_gtrg_1	std_logic
sr14_cnt	std_logic_vector ( 15 downto 0 )
sr15_cnt	std_logic_vector ( 15 downto 0 )
m4_out	std_logic
m4_out_clk	std_logic
m2_out	std_logic
m2_out_clk	std_logic
lctrqst_inner	std_logic
callct_1	std_logic
callct_2	std_logic
callct_3	std_logic
callct_inner	std_logic
pedestal_inner	std_logic
xl1adly_inner	std_logic_vector ( 1 downto 0 )

Instantiations
fdce_finj	fdce
fdc_preinj1	fdc
fdce_fpls	fdce
fdc_prepls_1	fdc
fdc_logich_frominj	fdc
fdc_inj_1	fdc
fd_inj_3	fd
fd_inj_4	fd
fd_1_inj_4	fd_1
fdc_logich_frompls	fdc
fdc_pls_1	fdc
fd_pls_3	fd
fd_pls_4	fd
fd_1_pls_4	fd_1
fd_rstplscnt	fd
fdc_logich_frominjpls	fdc
fdr_injpls_1	fdr
fd_callct_1	fd
fd_callct_3	fd
lctdly_gtrg	LCTDLY <Entity LCTDLY>

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The documentation for this class was generated from the following file:

• /homes/oshiro/odmb/firmware/odmb7_ucsb_dev/source/odmb_ctrl/calibtrg.vhd