voltage_mon_arch Architecture Reference

Processes
processmon	( CLK )
processdout	( CLK )
negedgecs_flop	( CLK )

Constants
START	std_logic := ' 1 '
STARTCHANNEL	std_logic_vector ( 2 downto 0 ) := " 000 "
RNG	std_logic := ' 1 '
BIP	std_logic := ' 0 '
PD1	std_logic := ' 0 '
PD0	std_logic := ' 1 '

Types
monstates	is ( S_MON_IDLE , S_MON_ASSCS1 , S_MON_CTRLSEQ , S_MON_WAIT )
doutstates	is ( S_DOUT_IDLE , S_DOUT_WAIT , S_DOUT_DATA )

Signals
current_channel	std_logic_vector ( 2 downto 0 ) := " 000 "
mon_SpiCsB	std_logic := ' 1 '
SpiCsB_N	std_logic
mon_start	std_logic := ' 0 '
mon_cmdcounter	std_logic_vector ( 7 downto 0 ) := x " 00 "
mon_cmdreg	std_logic_vector ( 7 downto 0 ) := x " 00 "
mon_inprogress	std_logic := ' 0 '
ctrlseq_done	std_logic := ' 0 '
data_done	std_logic := ' 0 '
data_valid	std_logic := ' 0 '
data_valid_cntr	std_logic_vector ( 7 downto 0 ) := x " 00 "
dout_data	std_logic_vector ( 11 downto 0 ) := x " 000 "
dout_counter	std_logic_vector ( 7 downto 0 ) := x " 00 "
variousflags	std_logic_vector ( 7 downto 0 ) := x " 00 "
ila_trigger1	std_logic_vector ( 7 downto 0 ) := x " 00 "
monstate	monstates := S_MON_IDLE
doutstate	doutstates := S_DOUT_IDLE

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The documentation for this class was generated from the following file:

• /homes/oshiro/odmb/firmware/odmb7_ucsb_dev/source/odmb_vme/voltage_mon.vhd