behavioral Architecture Reference

Processes
processread	( Clk )
processerase	( Clk )
processProgram	( Clk )
MuxMosi_int	( wrstate )
MuxMosi	( CLK )
MuxCsB	( Clk )
PROCESS_4	( clk )

Components
SpiCsBflop	<Entity SpiCsBflop>
oneshot	<Entity oneshot>
writeSpiFIFO

Constants
AddrWidth	integer := 32
SectorSize	integer := 65536
SizeSector	std_logic_vector ( 31 downto 0 ) := X " 00010000 "
SubSectorSize	integer := 4096
SizeSubSector	std_logic_vector ( 31 downto 0 ) := X " 00001000 "
NumberofSectors	std_logic_vector ( 8 downto 0 ) := " 000000000 "
PageSize	std_logic_vector ( 31 downto 0 ) := X " 00000100 "
NumberofPages	std_logic_vector ( 16 downto 0 ) := " 10000000000000000 "
AddrStart32	std_logic_vector ( 31 downto 0 ) := X " 00000000 "
AddrEnd32	std_logic_vector ( 31 downto 0 ) := X " 01FFFFFF "
Idcode25NQ256	std_logic_vector ( 23 downto 0 ) := X " 20BB19 "
CmdREAD24	std_logic_vector ( 7 downto 0 ) := X " 03 "
CmdFASTREAD	std_logic_vector ( 7 downto 0 ) := X " 0B "
CmdREAD32	std_logic_vector ( 7 downto 0 ) := X " 13 "
CmdRDID	std_logic_vector ( 7 downto 0 ) := X " 9F "
CmdRDFlashPara	std_logic_vector ( 7 downto 0 ) := X " 5A "
CmdRDFR24Quad	std_logic_vector ( 7 downto 0 ) := X " 0C "
CmdFLAGStatus	std_logic_vector ( 7 downto 0 ) := X " 70 "
CmdStatus	std_logic_vector ( 7 downto 0 ) := X " 05 "
CmdWE	std_logic_vector ( 7 downto 0 ) := X " 06 "
CmdSE24	std_logic_vector ( 7 downto 0 ) := X " D8 "
CmdSE32	std_logic_vector ( 7 downto 0 ) := X " DC "
CmdSSE24	std_logic_vector ( 7 downto 0 ) := X " 20 "
CmdSSE32	std_logic_vector ( 7 downto 0 ) := X " 21 "
CmdPP24	std_logic_vector ( 7 downto 0 ) := X " 02 "
CmdPP32	std_logic_vector ( 7 downto 0 ) := X " 12 "
CmdPP24Quad	std_logic_vector ( 7 downto 0 ) := X " 32 "
CmdPP32Quad	std_logic_vector ( 7 downto 0 ) := X " 34 "
Cmd4BMode	std_logic_vector ( 7 downto 0 ) := X " B7 "
CmdExit4BMode	std_logic_vector ( 7 downto 0 ) := X " E9 "

Types
erstates	is ( S_ER_IDLE , S_S4BMode_ASSCS1 , S_S4BMode_WRCMD , S_S4BMode_ASSCS2 , S_S4BMode_WR4BADDR , S_ER_ASSCS1 , S_ER_ASSCS2 , S_ER_ASSCS3 , S_ER_WRCMD , S_ER_ERASECMD , S_ER_RDSTAT )
wrstates	is ( S_WR_IDLE , S_WR_ASSCS1 , S_WR_WRCMD , S_WR_S4BMode_ASSCS1 , S_WR_S4BMode_WRCMD , S_WR_S4BMode_ASSCS2 , S_WR_S4BMode_WR4BADDR , S_WR_ASSCS2 , S_WR_PROGRAM , S_WR_DATA , S_WR_PPDONE , S_WR_PPDONEPRE , S_WR_PPDONESTATUS , S_WR_PPDONE_WAIT , S_EXIT4BMode_ASSCS1 , S_EXIT4BMODE )
rdstates	is ( S_RD_IDLE , S_RD_S4BMode_ASSCS1 , S_RD_S4BMode_WRCMD , S_RD_S4BMode_ASSCS2 , S_RD_S4BMode_WR4BADDR , S_RD_CS1 , S_RD_RDCMD , S_RD_EXIT4BMode_ASSCS1 , S_RD_EXIT4BMode )

Signals
CmdIndex	std_logic_vector ( 3 downto 0 ) := " 0001 "
CmdSelect	std_logic_vector ( 7 downto 0 ) := x " FF "
AddSelect	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
cmdcounter32	std_logic_vector ( 5 downto 0 ) := " 100111 "
cmdreg32	std_logic_vector ( 39 downto 0 ) := X " 1111111111 "
data_valid_cntr	std_logic_vector ( 2 downto 0 ) := " 000 "
rddata	std_logic_vector ( 1 downto 0 ) := " 00 "
wrdata_count	std_logic_vector ( 2 downto 0 ) := " 000 "
spi_wrdata	std_logic_vector ( 31 downto 0 ) := X " 00000000 "
page_count	std_logic_vector ( 17 downto 0 ) := " 111111111111111111 "
Current_Addr	std_logic_vector ( 31 downto 0 ) := X " 00000000 "
StatusDataValid	std_logic := ' 0 '
spi_status	std_logic_vector ( 1 downto 0 ) := " 11 "
write_done	std_logic := ' 0 '
write_nwords_limit	unsigned ( 13 downto 0 ) := ( others = > ' 0 ' )
er_sector_count	std_logic_vector ( 13 downto 0 ) := " 00000000000001 "
er_current_sector_addr	std_logic_vector ( 31 downto 0 ) := X " 00000000 "
er_SpiCsB	std_logic
erase_start	std_logic := ' 0 '
er_data_valid_cntr	std_logic_vector ( 2 downto 0 ) := " 000 "
er_cmdcounter32	std_logic_vector ( 5 downto 0 ) := " 111111 "
er_rddata	std_logic_vector ( 1 downto 0 ) := " 00 "
er_cmdreg32	std_logic_vector ( 39 downto 0 ) := X " 1111111111 "
er_status	std_logic_vector ( 1 downto 0 ) := " 11 "
erase_inprogress	std_logic := ' 0 '
erase_done	std_logic := ' 0 '
rd_SpiCsB	std_logic
read_start	std_logic := ' 0 '
read_done	std_logic := ' 1 '
rd_data_valid	std_logic := ' 0 '
rd_data_valid_cntr	std_logic_vector ( 3 downto 0 ) := " 0000 "
rd_current_sector_addr	std_logic_vector ( 31 downto 0 ) := X " 00000000 "
rd_nword_limit	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
rd_nword_cntr	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
rd_nword_cntr_dly	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
rd_data_wait_clk	integer := 48
rd_cmdcounter32	std_logic_vector ( 5 downto 0 ) := " 111111 "
rd_rddata	std_logic_vector ( 15 downto 0 ) := X " 0000 "
rd_rddata_all	std_logic_vector ( 15 downto 0 ) := X " 0000 "
rd_cmdreg32	std_logic_vector ( 39 downto 0 ) := X " 1111111111 "
read_inprogress	std_logic := ' 0 '
SpiMiso	std_logic
SpiMosi	std_logic
SpiCsB	std_logic := ' 1 '
SpiCsB_N	std_logic
SpiCsB_FFDin	std_logic := ' 1 '
di_out	std_logic_vector ( 3 downto 0 ) := X " 0 "
do_in	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
dopin_ts	std_logic_vector ( 3 downto 0 ) := " 1110 "
SpiMosi_int	std_logic
fifo_rden	std_logic := ' 0 '
fifo_empty	std_logic := ' 0 '
fifo_full	std_logic := ' 0 '
fifo_almostfull	std_logic := ' 0 '
fifo_almostempty	std_logic := ' 0 '
fifodout	std_logic_vector ( 63 downto 0 ) := X " 0000000000000000 "
fifo_unconned	std_logic_vector ( 15 downto 0 ) := X " 0000 "
reset_design	std_logic := ' 0 '
wrerr	std_logic := ' 0 '
rderr	std_logic := ' 0 '
synced_fifo_almostfull	std_logic_vector ( 1 downto 0 ) := " 00 "
synced_read	std_logic_vector ( 1 downto 0 ) := " 00 "
synced_erase	std_logic_vector ( 1 downto 0 ) := " 00 "
erstate	erstates := S_ER_IDLE
wrstate	wrstates := S_WR_IDLE
rdstate	rdstates := S_RD_IDLE

Attributes
mark_debug	string
dont_touch	string
keep	string
shreg_extract	string
async_reg	string
keep	synced_fifo_almostfull : signal is " true "
async_reg	synced_fifo_almostfull : signal is " true "
shreg_extract	synced_fifo_almostfull : signal is " no "
keep	synced_read : signal is " true "
async_reg	synced_read : signal is " true "
shreg_extract	synced_read : signal is " no "
keep	synced_erase : signal is " true "
async_reg	synced_erase : signal is " true "
shreg_extract	synced_erase : signal is " no "

Instantiations
startupe3_inst	startupe3
negedgecs_flop	SpiCsBflop <Entity SpiCsBflop>
oneshot_inst_rd	oneshot <Entity oneshot>
oneshot_inst_er	oneshot <Entity oneshot>
writefifo_i	writespififo

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The documentation for this class was generated from the following files:

• /homes/oshiro/odmb/firmware/odmb7_ucsb_dev/source/spi/spiflashprogrammer_test.vhd