ODMB7_UCSB_DEV
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behavioral Architecture Reference

Processes

update_chipsel  ( CLK )
mux_mosi  ( CLK )
mux_cs_bar  ( CLK )
process_read  ( CLK )
process_erase  ( CLK )
process_write  ( CLK )
process_erase_lock  ( CLK )
process_write_lock  ( CLK )
process_read_lock  ( CLK )
process_write_config  ( CLK )
process_read_register  ( CLK )
process_read_id  ( CLK )
process_clear_status  ( CLK )
process_custom  ( CLK )

Components

oneshot  <Entity oneshot>
writeSpiFIFO 

Constants

AddrWidth  integer := 32
SectorSize  integer := 65536
SizeSector  std_logic_vector ( 31 downto 0 ) := X " 00010000 "
SubSectorSize  integer := 4096
SizeSubSector  std_logic_vector ( 31 downto 0 ) := X " 00001000 "
NumberofSectors  std_logic_vector ( 8 downto 0 ) := " 000000000 "
PageSize  std_logic_vector ( 31 downto 0 ) := X " 00000100 "
NumberofPages  std_logic_vector ( 16 downto 0 ) := " 10000000000000000 "
AddrStart32  std_logic_vector ( 31 downto 0 ) := X " 00000000 "
AddrEnd32  std_logic_vector ( 31 downto 0 ) := X " 01FFFFFF "
Idcode25NQ256  std_logic_vector ( 23 downto 0 ) := X " 20BB19 "
CmdREAD24  std_logic_vector ( 7 downto 0 ) := X " 03 "
CmdFASTREAD  std_logic_vector ( 7 downto 0 ) := X " 0B "
CmdREAD32  std_logic_vector ( 7 downto 0 ) := X " 13 "
CmdRDID  std_logic_vector ( 7 downto 0 ) := X " 9F "
CmdRDFlashPara  std_logic_vector ( 7 downto 0 ) := X " 5A "
CmdRDFR24Quad  std_logic_vector ( 7 downto 0 ) := X " 0C "
CmdFLAGStatus  std_logic_vector ( 7 downto 0 ) := X " 70 "
CmdStatus  std_logic_vector ( 7 downto 0 ) := X " 05 "
CmdWE  std_logic_vector ( 7 downto 0 ) := X " 06 "
CmdSE24  std_logic_vector ( 7 downto 0 ) := X " D8 "
CmdSE32  std_logic_vector ( 7 downto 0 ) := X " DC "
CmdSSE24  std_logic_vector ( 7 downto 0 ) := X " 20 "
CmdSSE32  std_logic_vector ( 7 downto 0 ) := X " 21 "
CmdPP24  std_logic_vector ( 7 downto 0 ) := X " 02 "
CmdPP32  std_logic_vector ( 7 downto 0 ) := X " 12 "
CmdPP24Quad  std_logic_vector ( 7 downto 0 ) := X " 32 "
CmdPP32Quad  std_logic_vector ( 7 downto 0 ) := X " 34 "
Cmd4BMode  std_logic_vector ( 7 downto 0 ) := X " B7 "
CmdExit4BMode  std_logic_vector ( 7 downto 0 ) := X " E9 "
CmdEraseNonvLock  std_logic_vector ( 7 downto 0 ) := X " E4 "
CmdWriteNonvLock  std_logic_vector ( 7 downto 0 ) := X " E3 "
CmdWriteVolaLock  std_logic_vector ( 7 downto 0 ) := X " E5 "
CmdReadVolaLock  std_logic_vector ( 7 downto 0 ) := X " E8 "
CmdReadNonvLock  std_logic_vector ( 7 downto 0 ) := X " E2 "
CmdWriteNonvConfig  std_logic_vector ( 7 downto 0 ) := X " B1 "
CmdWriteVolaConfig  std_logic_vector ( 7 downto 0 ) := X " 81 "
CmdWriteExteConfig  std_logic_vector ( 7 downto 0 ) := X " 61 "
CmdWriteStatus  std_logic_vector ( 7 downto 0 ) := X " 01 "
CmdReadNonvConf  std_logic_vector ( 7 downto 0 ) := X " B5 "
CmdReadVolaConf  std_logic_vector ( 7 downto 0 ) := X " 85 "
CmdReadExteConf  std_logic_vector ( 7 downto 0 ) := X " 65 "
CmdClearFlagStatus  std_logic_vector ( 7 downto 0 ) := X " 50 "
custom_enable  std_logic := ' 1 '

Types

write_states is ( S_WRITE_IDLE , S_WRITE_ASSERT_CS_WRITE_ENABLE , S_WRITE_SHIFT_WRITE_ENABLE , S_WRITE_ASSERT_CS_PROGRAM , S_WRITE_SHIFT_PROGRAM , S_WRITE_SHIFT_DATA , S_WRITE_ASSERT_CS_READ_STATUS , S_WRITE_SHIFT_READ_STATUS , S_WRITE_ASSERT_CS_READ_STATUS_2 , S_WRITE_SHIFT_READ_STATUS_2 )
read_states is ( S_READ_IDLE , S_READ_ASSERT_CS , S_READ_SHIFT_READ )
erase_states is ( S_ERASE_IDLE , S_ERASE_ASSERT_CS_WRITE_ENABLE , S_ERASE_SHIFT_WRITE_ENABLE , S_ERASE_ASSERT_CS_ERASE , S_ERASE_SHIFT_ERASE , S_ERASE_ASSERT_CS_READ_STATUS , S_ERASE_SHIFT_READ_STATUS )
erase_lock_states is ( S_ERASE_LOCK_IDLE , S_ERASE_LOCK_ASSERT_CS_WRITE_ENABLE , S_ERASE_LOCK_SHIFT_WRITE_ENABLE , S_ERASE_LOCK_ASSERT_CS_ERASE_LOCK , S_ERASE_LOCK_SHIFT_ERASE_LOCK , S_ERASE_LOCK_ASSERT_CS_READ_STATUS , S_ERASE_LOCK_SHIFT_READ_STATUS )
write_lock_states is ( S_WRITE_LOCK_IDLE , S_WRITE_LOCK_ASSERT_CS_WRITE_ENABLE , S_WRITE_LOCK_SHIFT_WRITE_ENABLE , S_WRITE_LOCK_ASSERT_CS_WRITE_LOCK , S_WRITE_LOCK_SHIFT_WRITE_LOCK , S_WRITE_LOCK_ASSERT_CS_READ_STATUS , S_WRITE_LOCK_SHIFT_READ_STATUS , S_WRITE_LOCK_ASSERT_CS_READ_STATUS_2 , S_WRITE_LOCK_SHIFT_READ_STATUS_2 )
write_config_states is ( S_WRITE_CONFIG_IDLE , S_WRITE_CONFIG_ASSERT_CS_WRITE_ENABLE , S_WRITE_CONFIG_SHIFT_WRITE_ENABLE , S_WRITE_CONFIG_ASSERT_CS_WRITE_CONFIG , S_WRITE_CONFIG_SHIFT_WRITE_CONFIG , S_WRITE_CONFIG_ASSERT_CS_READ_STATUS , S_WRITE_CONFIG_SHIFT_READ_STATUS , S_WRITE_CONFIG_ASSERT_CS_READ_STATUS_2 , S_WRITE_CONFIG_SHIFT_READ_STATUS_2 )
read_register_states is ( S_READ_REGISTER_IDLE , S_READ_REGISTER_ASSERT_CS_READ , S_READ_REGISTER_SHIFT_READ )
read_id_states is ( S_READ_ID_IDLE , S_READ_ID_ASSERT_CS_READ , S_READ_ID_SHIFT_READ )
read_lock_states is ( S_READ_LOCK_IDLE , S_READ_LOCK_ASSERT_CS_READ , S_READ_LOCK_SHIFT_READ )
clear_status_states is ( S_CLEAR_STATUS_IDLE , S_CLEAR_STATUS_ASSERT_CS , S_CLEAR_STATUS_SHIFT )
custom_states is ( S_CUSTOM_IDLE , S_CUSTOM_ASSERT_CS , S_CUSTOM_SHIFT , S_CUSTOM_FLUSH_FIFO )

Signals

spi_miso  std_logic
spi_mosi  std_logic
spi_cs_bar  std_logic
spi_cs_bar_input  std_logic := ' 1 '
spi_cs_bar_delay  std_logic := ' 1 '
di_out  std_logic_vector ( 3 downto 0 ) := X " 0 "
do_in  std_logic_vector ( 3 downto 0 ) := " 0000 "
qspi_io  std_logic_vector ( 3 downto 1 ) := " 111 "
dopin_ts  std_logic_vector ( 3 downto 0 ) := " 1110 "
write_fifo_output  std_logic_vector ( 3 downto 0 ) := " 0000 "
write_spi_fifo_read_enable  std_logic := ' 0 '
write_fifo_read_enable  std_logic := ' 0 '
read_spi_cs_bar  std_logic := ' 1 '
read_done  std_logic := ' 1 '
read_word_limit  unsigned ( 31 downto 0 ) := x " 00000000 "
read_word_counter  unsigned ( 31 downto 0 ) := x " 00000000 "
read_data  std_logic_vector ( 15 downto 0 ) := X " 0000 "
read_data_valid  std_logic := ' 0 '
read_data_counter  std_logic_vector ( 3 downto 0 ) := " 0000 "
read_address  std_logic_vector ( 31 downto 0 ) := X " 00000000 "
read_cmdcounter  unsigned ( 5 downto 0 ) := " 111111 "
read_cmdreg  std_logic_vector ( 39 downto 0 ) := X " 1111111111 "
erase_spi_cs_bar  std_logic := ' 1 '
erase_done  std_logic := ' 1 '
erase_address  std_logic_vector ( 31 downto 0 ) := x " 00000000 "
erase_cmdcounter  unsigned ( 5 downto 0 ) := " 111111 "
erase_cmdreg  std_logic_vector ( 39 downto 0 ) := x " 1111111111 "
erase_status_bit_index  std_logic_vector ( 7 downto 0 ) := x " 00 "
write_spi_cs_bar  std_logic := ' 1 '
write_done  std_logic := ' 1 '
write_address  std_logic_vector ( 31 downto 0 ) := x " 00000000 "
write_cmdcounter  unsigned ( 5 downto 0 ) := " 111111 "
write_cmdreg  std_logic_vector ( 39 downto 0 ) := x " 1111111111 "
write_word_limit  unsigned ( 31 downto 0 ) := x " 00000000 "
write_data_counter  unsigned ( 1 downto 0 ) := " 00 "
write_word_counter  unsigned ( 31 downto 0 ) := x " 00000000 "
write_status_bit_index  std_logic_vector ( 7 downto 0 ) := x " 00 "
erase_lock_spi_cs_bar  std_logic := ' 1 '
erase_lock_done  std_logic := ' 1 '
erase_lock_cmdcounter  unsigned ( 5 downto 0 ) := " 111111 "
erase_lock_cmdreg  std_logic_vector ( 39 downto 0 ) := x " 1111111111 "
erase_lock_status_bit_index  std_logic_vector ( 7 downto 0 ) := x " 00 "
write_lock_spi_cs_bar  std_logic := ' 1 '
write_lock_type  std_logic_vector ( 1 downto 0 ) := " 00 "
write_lock_address  std_logic_vector ( 31 downto 0 ) := x " 00000000 "
write_lock_address_volatile  std_logic_vector ( 31 downto 0 ) := x " 00000000 "
write_lock_done  std_logic := ' 1 '
write_lock_cmdcounter  unsigned ( 5 downto 0 ) := " 111111 "
write_lock_cmdreg  std_logic_vector ( 39 downto 0 ) := x " 1111111111 "
write_lock_status_bit_index  std_logic_vector ( 7 downto 0 ) := x " 00 "
read_lock_spi_cs_bar  std_logic := ' 1 '
read_lock_type  std_logic_vector ( 1 downto 0 ) := " 00 "
read_lock_address  std_logic_vector ( 31 downto 0 ) := x " 00000000 "
read_lock_address_volatile  std_logic_vector ( 31 downto 0 ) := x " 00000000 "
read_lock_done  std_logic := ' 0 '
read_lock_cmdcounter  unsigned ( 5 downto 0 ) := " 000000 "
read_lock_cmdreg  std_logic_vector ( 39 downto 0 ) := x " 0000000000 "
read_lock_data_counter  unsigned ( 1 downto 0 ) := " 00 "
read_lock_data  std_logic_vector ( 15 downto 0 ) := x " 0000 "
read_lock_data_valid  std_logic := ' 0 '
write_config_spi_cs_bar  std_logic := ' 1 '
write_config_done  std_logic := ' 1 '
write_config_cmdcounter  unsigned ( 5 downto 0 ) := " 111111 "
write_config_cmdreg  std_logic_vector ( 39 downto 0 ) := x " 1111111111 "
write_config_status_bit_index  std_logic_vector ( 7 downto 0 ) := x " 00 "
write_register_type  std_logic_vector ( 3 downto 0 ) := x " 0 "
read_register_spi_cs_bar  std_logic := ' 1 '
read_register_done  std_logic := ' 0 '
read_register_type  std_logic_vector ( 3 downto 0 ) := x " 0 "
read_register_bit_index  std_logic_vector ( 7 downto 0 ) := x " 00 "
read_register_cmdcounter  unsigned ( 5 downto 0 ) := " 111111 "
read_register_cmdreg  std_logic_vector ( 39 downto 0 ) := x " 1111111111 "
register_inner  std_logic_vector ( 7 downto 0 ) := x " 00 "
register_we  std_logic := ' 0 '
read_register_max_index  std_logic_vector ( 7 downto 0 ) := x " 00 "
read_id_spi_cs_bar  std_logic := ' 1 '
read_id_done  std_logic := ' 0 '
read_id_cmdcounter  unsigned ( 5 downto 0 ) := " 111111 "
read_id_cmdreg  std_logic_vector ( 39 downto 0 ) := x " 1111111111 "
read_id_data  std_logic_vector ( 15 downto 0 ) := x " 0000 "
read_id_data_valid  std_logic := ' 0 '
read_id_data_counter  unsigned ( 7 downto 0 ) := x " 00 "
clear_status_spi_cs_bar  std_logic := ' 1 '
clear_status_done  std_logic := ' 0 '
clear_status_cmdcounter  unsigned ( 5 downto 0 ) := " 111111 "
clear_status_cmdreg  std_logic_vector ( 39 downto 0 ) := x " 1111111111 "
custom_done  std_logic := ' 1 '
custom_spi_cs_bar  std_logic := ' 1 '
custom_fifo_read_enable  std_logic := ' 0 '
custom_nbits_write  unsigned ( 10 downto 0 ) := " 00000000000 "
custom_nwords_read  unsigned ( 15 downto 0 ) := x " 0000 "
custom_mosi  std_logic := ' 0 '
custom_fifo_idx  unsigned ( 1 downto 0 ) := " 11 "
custom_data_counter  unsigned ( 3 downto 0 ) := x " 0 "
custom_data  std_logic_vector ( 15 downto 0 ) := x " 0000 "
custom_data_valid  std_logic := ' 0 '
custom_first_read_cycle  std_logic := ' 0 '
write_state  write_states := S_WRITE_IDLE
read_state  read_states := S_READ_IDLE
erase_state  erase_states := S_ERASE_IDLE
erase_lock_state  erase_lock_states := S_ERASE_LOCK_IDLE
write_lock_state  write_lock_states := S_WRITE_LOCK_IDLE
write_config_state  write_config_states := S_WRITE_CONFIG_IDLE
read_register_state  read_register_states := S_READ_REGISTER_IDLE
read_id_state  read_id_states := S_READ_ID_IDLE
read_lock_state  read_lock_states := S_READ_LOCK_IDLE
clear_status_state  clear_status_states := S_CLEAR_STATUS_IDLE
custom_state  custom_states := S_CUSTOM_IDLE

Attributes

mark_debug  string
dont_touch  string
keep  string
shreg_extract  string
async_reg  string

Instantiations

startupe3_inst  startupe3
writefifo_i  writespififo
The documentation for this class was generated from the following files:
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