SYSTEM_TEST_Arch Architecture Reference

Processes
prbs_tx_cnt_proc	( CLK , RST , otmb_prbs_tx_en , otmb_prbs_cnt_rst , otmb_tx_good_cntr_int , otmb_prbs_tx_err , otmb_tx_err_cntr , otmb_tx_good_cntr )

Components
PRBS_GEN	<Entity PRBS_GEN>

Constants
dcfeb_prbs_rst_cycles	integer := 1
dcfeb_prbs_lock	integer := 20000000
dcfeb_prbs_length	integer := 119
otmb_prbs_length	integer := 10000

Signals
ila_data	std_logic_vector ( 383 downto 0 ) := ( others = > ' 0 ' )
outdata_inner	std_logic_vector ( 15 downto 0 )
dtack_inner	std_logic
cmddev	std_logic_vector ( 15 downto 0 )
w_ddu_prbs_tx_en	std_logic
w_pc_prbs_tx_en	std_logic
w_ddu_prbs_rx_en	std_logic
w_pc_prbs_rx_en	std_logic
r_ddu_prbs_err_cnt	std_logic
r_pc_prbs_err_cnt	std_logic
strobe_pulse	std_logic
r_prbs_type	std_logic
w_prbs_type	std_logic
prbs_type_inner	std_logic_vector ( 3 downto 0 )
w_dcfeb_prbs_en	std_logic
r_dcfeb_prbs_err_cnt	std_logic
w_dcfeb_prbs_fiber	std_logic
r_dcfeb_prbs_fiber	std_logic
r_dcfeb_prbs_edge	std_logic
dcfeb_prbs_fiber_sel_inner	std_logic_vector ( 3 downto 0 )
dcfeb_prbs_rst_cnt	integer
dcfeb_prbs_seq_cnt	std_logic_vector ( 15 downto 0 )
dcfeb_prbs_en_cnt	integer
dcfeb_prbs_rd_en_cnt	integer
dcfeb_prbserr_edge_cnt	std_logic_vector ( 15 downto 0 )
dcfeb_prbs_init_pulse	std_logic
dcfeb_prbs_reset_pulse	std_logic
dcfeb_prbs_rd_en_pulse	std_logic
dcfeb_prbs_en_pulse	std_logic
start_otmb_prbs_rx	std_logic
pulse_otmb_prbs_tx_end	std_logic
otmb_prbs_tx_rst	std_logic
otmb_prbs_rx_rst	std_logic
otmb_prbs_tx_en	std_logic
otmb_prbs_tx_en_b	std_logic
pulse_otmb_prbs_rx_end	std_logic
otmb_prbs_tx_xor	std_logic_vector ( 48 downto 0 )
otmb_prbs_tx	std_logic
otmb_prbs_tx_err	std_logic
w_otmb_prbs_en	std_logic
r_otmb_prbs_err_cnt	std_logic
r_otmb_prbs_good_cnt	std_logic
otmb_prbs_rx_cycles	integer
otmb_prbs_rx_sequences	std_logic_vector ( 15 downto 0 )
otmb_prbs_rx_en	std_logic
otmb_prbs_rx_en_b	std_logic
otmb_prbs_rx	std_logic
otmb_rx_inner	std_logic_vector ( 5 downto 0 )
otmb_tx_err_cntr	integer
otmb_tx_err_cnt	std_logic_vector ( 15 downto 0 )
q_otmb_prbs_tx_en	std_logic
q_otmb_prbs_tx_en_b	std_logic
qq_otmb_prbs_tx_en	std_logic
mux_otmb_tx	std_logic_vector ( 48 downto 0 )
q_otmb_tx	std_logic_vector ( 48 downto 0 )
otmb_prbs_cnt_rst	std_logic
w_otmb_prbs_cnt_rst	std_logic
otmb_tx_good_cntr	integer
otmb_tx_good_cntr_int	integer
otmb_tx_good_cnt	std_logic_vector ( 15 downto 0 )
otmb_prbs_tx_en_cnt	std_logic_vector ( 15 downto 0 )
r_otmb_prbs_en_cnt	std_logic

Instantiations
strobe_pe	PULSE_EDGE <Entity PULSE_EDGE>
fdc_ddu_tx_prbs	fdc
fdc_pc_tx_prbs	fdc
fdc_ddu_prbs	fdc
fdc_pc_prbs	fdc
fdc_dcfeb_prbs	fdc
fdc_otmb_prbs	fdc
fdc_fiber	fdc
fdc_prbs_sel	fdc
dcfebprbsinit	PULSE_EDGE <Entity PULSE_EDGE>
dcfebprbsrst	PULSE_EDGE <Entity PULSE_EDGE>
dcfebprbsrden	PULSE_EDGE <Entity PULSE_EDGE>
dcfebprbsen	PULSE_EDGE <Entity PULSE_EDGE>
prbserr_cnt	COUNT_EDGES <Entity COUNT_EDGES>
fd_otmb_start	fd
pulseotmb_en	PULSE_EDGE <Entity PULSE_EDGE>
pulseotmb_rx_rst	PULSE_EDGE <Entity PULSE_EDGE>
prbs_gen_pm	PRBS_GEN <Entity PRBS_GEN>
tx_en_cnt	COUNT_EDGES <Entity COUNT_EDGES>
pulseotmb_tx_rst	PULSE_EDGE <Entity PULSE_EDGE>
pe_en	PULSE_EDGE <Entity PULSE_EDGE>
pe_en2	PULSE_EDGE <Entity PULSE_EDGE>
prbs_gen_tx_pm	PRBS_GEN <Entity PRBS_GEN>
fd_otmb_tx	fd
cnt_rst	PULSE_EDGE <Entity PULSE_EDGE>

---

The documentation for this class was generated from the following files:

• /homes/oshiro/odmb/firmware/odmb7_ucsb_dev/source/odmb_vme/system_test.vhd