SPI_PORT_Arch Architecture Reference

Processes
reset_proc	( SLOWCLK )
spi_read_proc	( SLOWCLK )
cfg_write_proc	( SLOWCLK )
const_write_proc	( SLOWCLK )
cfg_upload_proc	( SLOWCLK )
const_upload_proc	( SLOWCLK )

Types
cfg_download_states	is ( S_IDLE , S_SET_ADDR_LOWER , S_ERASE , S_BUFFER_PROGRAM , S_WRITE )
cfg_upload_states	is ( S_IDLE , S_SET_ADDR_LOWER , S_READN , S_WAIT_READ_BUSY , S_WAIT_READ_DONE , S_WAIT_READ_STALL , S_READBACK )
rst_upload_states	is ( S_IDLE , S_WAIT , S_CFG_PULSE , S_CFG_WAIT , S_CONST_PULSE , S_CONST_WAIT )

Signals
cfg_download_state	cfg_download_states := S_IDLE
spi_cmd_fifo_write_en_cfg_dl	std_logic := ' 0 '
spi_cmd_fifo_in_cfg_dl	std_logic_vector ( 15 downto 0 ) := x " 0000 "
download_cfg_reg_index	integer := 0
const_download_state	cfg_download_states := S_IDLE
spi_cmd_fifo_write_en_const_dl	std_logic := ' 0 '
spi_cmd_fifo_in_const_dl	std_logic_vector ( 15 downto 0 ) := x " 0000 "
download_const_reg_index	integer := 0
cfg_upload_state	cfg_upload_states := S_IDLE
spi_cmd_fifo_write_en_cfg_ul	std_logic := ' 0 '
spi_cmd_fifo_in_cfg_ul	std_logic_vector ( 15 downto 0 ) := x " 0000 "
upload_cfg_reg_index	integer := 0
spi_readback_fifo_read_en_cfg_ul	std_logic := ' 0 '
spi_cfg_ul_pulse_inner	std_logic := ' 0 '
spi_cfg_reg_we_inner	integer := NREGS
spi_cfg_ul_reg	std_logic_vector ( 15 downto 0 ) := x " 0000 "
cfg_readback_fifo_stall_counter	unsigned ( 7 downto 0 ) := x " FF "
const_upload_state	cfg_upload_states := S_IDLE
spi_cmd_fifo_write_en_const_ul	std_logic := ' 0 '
spi_cmd_fifo_in_const_ul	std_logic_vector ( 15 downto 0 ) := x " 0000 "
upload_const_reg_index	integer := 0
spi_readback_fifo_read_en_const_ul	std_logic := ' 0 '
spi_const_ul_pulse_inner	std_logic := ' 0 '
spi_const_reg_we_inner	integer := NREGS
spi_const_ul_reg	std_logic_vector ( 15 downto 0 ) := x " 0000 "
const_readback_fifo_stall_counter	unsigned ( 7 downto 0 ) := x " FF "
ul_dl_busy	std_logic := ' 0 '
strobe_meta	std_logic := ' 0 '
strobe_q	std_logic := ' 0 '
strobe_qq	std_logic := ' 0 '
strobe_pulse	std_logic := ' 0 '
spi_cmd_fifo_write_en_cmd	std_logic := ' 0 '
spi_cmd_fifo_in_cmd	std_logic_vector ( 15 downto 0 ) := x " 0000 "
spi_read_data	std_logic_vector ( 15 downto 0 ) := x " 0000 "
spi_readback_fifo_read_en_cmd	std_logic := ' 0 '
cmddev	std_logic_vector ( 15 downto 0 ) := x " 0000 "
do_cfg_read	std_logic := ' 0 '
do_cfg_write	std_logic := ' 0 '
do_const_read	std_logic := ' 0 '
do_const_write	std_logic := ' 0 '
do_spi_cmd	std_logic := ' 0 '
do_spi_read	std_logic := ' 0 '
do_read_readback_fifo_nwords	std_logic := ' 0 '
do_reset_spi_fsm	std_logic := ' 0 '
do_enable_spi_fsm	std_logic := ' 0 '
do_disable_spi_fsm	std_logic := ' 0 '
do_read_timer_lsb	std_logic := ' 0 '
do_read_timer_msb	std_logic := ' 0 '
do_read_status	std_logic := ' 0 '
rst_upload_state	rst_upload_states := S_IDLE
rst_q	std_logic := ' 0 '
rst_pulse	std_logic := ' 0 '
rst_sync	std_logic := ' 0 '
rst_wait_counter	unsigned ( 7 downto 0 ) := x " 00 "
startup_cfg_read	std_logic := ' 0 '
startup_const_read	std_logic := ' 0 '
ce_d_dtack	std_logic := ' 0 '
d_dtack	std_logic := ' 0 '
q_dtack	std_logic := ' 0 '
outdata_inner	std_logic_vector ( 15 downto 0 ) := x " 0000 "
ila_probe	std_logic_vector ( 511 downto 0 ) := ( others = > ' 0 ' )

Instantiations
slowclk_domain_reset	PULSE2SLOW <Entity PULSE2SLOW>
fd_d_dtack	fdce
fd_q_dtack	fd

---

The documentation for this class was generated from the following files:

• /homes/oshiro/odmb/firmware/odmb7_ucsb_dev/source/odmb_vme/spi_port.vhd