Signals
BUSY	std_logic
WRITEADC	std_logic
READMON	std_logic
WRITEPOWER	std_logic
READPOWER	std_logic
READPOWERSTATUS	std_logic
SELADC	std_logic
READADC	std_logic
ce_seladc	std_logic := ' 0 '
ce_writepower	std_logic := ' 0 '
SELADC_vector	std_logic_vector ( 3 downto 1 )
LVTURNON_INNER	std_logic_vector ( 8 downto 1 )
D_OUTDATA	std_logic
Q_OUTDATA	std_logic
D_OUTDATA_2	std_logic
Q_OUTDATA_2	std_logic
D_DTACK_2	std_logic
Q_DTACK_2	std_logic
D_DTACK_4	std_logic
Q_DTACK_4	std_logic
dd_dtack	std_logic := ' 0 '
d_dtack	std_logic := ' 0 '
C_LOADON	std_logic
Q1_LOADON	std_logic
Q2_LOADON	std_logic
LOADON_INNER	std_logic
ADCCLK_INNER	std_logic
CE_ADCCLK	std_logic
CLR_ADCCLK	std_logic
RSTBUSY	std_logic
CLKMON	std_logic
CE1_BUSY	std_logic
CE2_BUSY	std_logic
CLR_BUSY	std_logic
Q1_BUSY	std_logic
Q2_BUSY	std_logic
D_BUSY	std_logic
DONEMON	std_logic
LOAD	std_logic
blank1	std_logic
blank2	std_logic
QTIME	std_logic_vector ( 7 downto 0 )
CLR1_LOAD	std_logic
CLR2_LOAD	std_logic
Q1_LOAD	std_logic
Q2_LOAD	std_logic
Q3_LOAD	std_logic
Q4_LOAD	std_logic
CE_LOAD	std_logic
ASYNLOAD	std_logic
q3_load_pulse	std_logic
asynload_q	std_logic
asynload_pulse	std_logic
RDMONBK	std_logic
CE_OUTDATA_FULL	std_logic
Q_OUTDATA_FULL	std_logic_vector ( 15 downto 0 )
SLI_ADCDATA	std_logic
L_ADCDATA	std_logic
CE_ADCDATA	std_logic
Q_ADCDATA	std_logic_vector ( 7 downto 0 )
cmddev	std_logic_vector ( 15 downto 0 )
strobe_q	std_logic
strobe_qq	std_logic
strobe_pulse	std_logic
diaglvdb_inner	std_logic_vector ( 17 downto 0 )

Instantiations
fd_outdata	fd
fdce_out	fdce
fd_dtack_2	fd
fdpe_out2	fdpe
fd_dtack_4	fd
fd_outdata_2	fd
fdc_loadon	fdce
fd_loadon1	fd
fd_loadon2	fd
fdce_adcclk	fdce
fdce_busy	fdce
fd_busy	fd
fdr_busy	fdr
fdc_vcc	fdce
fdc_load1	fdc
fdce_load2	fdce
fdc_load4	fdce

The documentation for this class was generated from the following file:

/homes/oshiro/odmb/firmware/odmb7_ucsb_dev/source/odmb_vme/lvdbmon.vhd

Signals

Instantiations