PULSE_EDGE_Arch Architecture Reference

Processes
pulse_fsm_regs	( CLK , RST , pulse_cnt_en , pulse_next_state )
pulse_fsm_logic	( pulse1_inner , pulse_current_state , pulse_cnt , NPULSE )

Types
pulse_state_type	is ( PULSE_IDLE , PULSE_COUNTING )

Signals
pulse1_inner	std_logic
pulse1_d	std_logic
pulse_cnt	integer := 1
pulse_cnt_en	std_logic := ' 0 '
reset_q	std_logic := ' 0 '
clk_pulse	std_logic := ' 0 '
pulse_next_state	pulse_state_type
pulse_current_state	pulse_state_type

Instantiations
fddin	fdc
fdpulse1_a	fd

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The documentation for this class was generated from the following files:

• /homes/oshiro/odmb/firmware/odmb7_ucsb_dev/source/utils/pulse_edge.vhd