PULSE2SLOW_Arch Architecture Reference

Signals
pulsein	std_logic_vector ( 0 to 1 )
pulse	std_logic_vector ( 2 to 4 )

Instantiations
fd1	fdc
fd2	fdc
fd3	fdc
fd4	fdc

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The documentation for this class was generated from the following file:

• /homes/oshiro/odmb/firmware/odmb7_ucsb_dev/source/utils/pulse2slow.vhd