Some suggestions
To reduce the drop of efficiency at large f’, one might consider using lower thresholds for the 2 chips at the right edge and 1 chip at the left edge of the HDI than for all the other chips.
The thresholds might have to be set at less than
4rnoise for the inner layers (Phi strips).
One should probably be testing SVT software at noise & thresholds 30% higher than nominal as well as at nominal settings.