Minutes of the May 26, 2005 US ROD meeting

Follow up on action items and new action items

1. Scripts to compare MR with module data:
   Steve has it working.
   Still fine-tuning of cuts needed. Steve will also look at FNAL data.
   Progress. FNAL data still to do. Problem with saturation in inv on mode.
   Traced to incorrect VPSP setting for calprof runs. This was fixed right after the meeting at both UCSB and FNAL.


2. UCSB: Sort out problem with bad lemo.
   Spares on the way from FNAL.
   Done.
   


3. UCSB: DS rod bad noise. But using modules that went through severe cycles.
   Need to put new modules on it and retest.
   On back-burner until modules become available.
   In the meantime take a couple of these modules off and see what they look like on ARCS.
   Look basically OK on ARCS, with lots of bad channles.
   Next: put DS rod back together, retest.
   Looks much better now. No more panic for now.
   


4. UCSB: Tests of rod 178 (header-error rod from FNAL) continue. Swap
   module that gives errors to try to correlate with either rod or module.
   Put this on back-burner now that production has started.
   


5. Lt SW bug that causes bad pulse shape. Valeri on it.
   May be OK if change parameters of CMN subtraction.
   Jim fixed at UCSB, need to propagate to FNAL.
   Still needs to be done at FNAL
   


6. FNAL: Tested bunch of new HPK rods in SR. Two out of six have broken or shorted
   termistor. Strange because Lenny says that these are chcked on rod frame.
   Possibilities: bad check on rod frame, or bad connection through flat cable, or bad DCU on hybrid.
   Check module fast-test
   Probe with multimeter
   No news
   


7. FNAL: some bad DCU voltrages on SR, but not on MR. Needs fix.
   Not clear. Wim committed fix.
   Check env, then PIA reset. Ryan to double-check
   
8. Javier has new DefectAnalyizer. Steve did not know about it.
   Get new code.
   Not yet
   


9. According to Sandro's email, there should be no
   I2C transactions in broadcast mode.
   Wim to fix Lt.
   



FNAL

Ryan: worked on rod 17 with FNAl engineers. At position 6
with R = 82 Ohm only a couple of nsec margin in timing between
clock and data. At position 2 the margin is mor elike 8 nsec,
probably because of different C due to buss length.
Basically agrees with Sandro's presentation from Tuesday

Yuri: test 2 rods with resistors modified.
SR: OK manually, errors on scenario.
MR: two diferent rods, OK manually AND in scenario.
With new resitors other devices reporting errors (MUX, PLL, DCU) on SR.